Abstract— Computational Private Information Retrieval (cPIR) protocols allow a client to retrieve one bit from a database, without the server inferring any information about the queried bit. These protocols are too costly in practice because they invoke complex arithmetic operations for every bit of the database. In this paper, we present pCloud, a distributed system that constitutes the first attempt toward practical cPIR. Our approach assumes a disk-based architecture that retrieves one page with a single query. Using a striping technique, ....etc

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Fastest Clock Speed up to 550 MHz and Total Data Rate up to 80
Gbps; Dramatically Expanding the Performance of Networking and Signal Processing
Applications Compared with 90-nm SRAMs, Cypresss 65-nm QDR and DDR SRAMs offer up to 50% lower standby and dynamic current consumption, enabling the new wave of green networking infrastructure applications. The QDRII+ and DDRII+ devices have
On-Die Termination (ODT), which improves signal integrity, reduces system cost,
and saves board space by eliminating external termination resistors. The 65-n ....etc

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hi iam mohammed i would like to get datails on vlsi projects sram ....etc

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ABSTRACT

Leakage power consumption is large fraction of the total power consumption in contemporary VLSI designs. Since memories occupy a large portion of the total area of many high-performance ICs, it is crucial to reduce the leakage energy of memories. This problem is particularly aggravated for memories implemented in the 45nm technology node, since these processes exhibit significantly higher leakage power. For these memories, leakage is a significant problem not only from a power point of view, but also from performance degradation st ....etc

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1. A Novel Carry-Look ahead Approach to an Unified BCD and Binary Adder/ Subtractor
2. Speculative Carry Generation with Prefix Adder Using VHDL / Verilog
3. Improving Error Tolerance For Multithreaded Register Files
4. Higher Radix and Redundancy Factor for Floating Point Sort Division using VHDL/ Verilog
5. Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores using VHDL
6. Reconfigurable Architecture for Network Flow Analysis
7. The Reconfigurable Instruction Cell Array
8. System Architecture and ....etc

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Benton Highsmith Calhoun, Member, IEEE, and Anantha P. Chandrakasan, Fellow, IEEE

Abstract—
Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the challenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six–transistor (6 T) SRAM and proposes an alternative bitcell that functions to much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chi ....etc

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hi sir/mam
i vijji, interested to know about advantages and disadvantages of 6t sram cell ....etc

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ABSTRACT


Data storage is a growing need in these days. With the advent of new technologies the concept of “more data in less space” is gaining importance day by day.

Most commonly used semiconductor memory is SRAM. Static Random Access Memory (SRAM) is a type of semiconductor memory where the word static indicates that unlike Dynamic RAM (DRAM) it does not need to be periodically refreshed, as SRAM is volatile in the conventional sense that data is eventu ....etc

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1. High Speed DDR- SDRM Controller With 64-Bit Data Transfer
2. Redundant Radix “ 4 Co-Processor For High Speed Arithmetic Operations
3. Implementation Of PHELIX For Fast Encryption & Authentication
4. Design & Implementation Of ATM Knock Out Switch Using Concentrator
5. SDR “ SDRM Controller With 64 - Bit Data Transfer
6. Implementation Of Jpeg Base Line Image Compression
7. Implementation Of 8 “ Bit Pico Processor To Perform Arithmetic & Logical Operations
8. Design Of Ethernet IP Core 802.3 And Implementation
9. Im ....etc

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kindly mail mini project topics along with the report n code for the above mentioned topic. THANK U ....etc

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