1. A Novel Carry-Look ahead Approach to an Unified BCD and Binary Adder/ Subtractor
2. Speculative Carry Generation with Prefix Adder Using VHDL / Verilog
3. Improving Error Tolerance For Multithreaded Register Files
4. Higher Radix and Redundancy Factor for Floating Point Sort Division using VHDL/ Verilog
5. Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores using VHDL
6. Reconfigurable Architecture for Network Flow Analysis
7. The Reconfigurable Instruction Cell Array
8. System Architecture and Implementation of MIMO Sphere Decoders on FPGA
9. Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
10. Register for Phase Difference Based Logic
11. Designing Efficient Online Testable Reversible Adder with New Reversible Gate
12. High Speed Recursion Architecture for Map- Based Turbo Decoders
13. Concurrent Error Detection in Reed Solomon Encoders and Decoders
14. LFSR-Reseeding Scheme Achieving Low-Power Dissipation during Test
15. FPGA Implementation of Low Power Parallel Multiplier
16. Low Power Multiplier with Superious Power Suppression Technique
17. Abstraction and Refinement Techniques in Automated Design Debugging
18. Concurrent Error Detection in Reed Solomon Encoders and Decoders
19. Implementation of AES on A Dynamically Reconfigurable Architecture
20. Designing Efficient Online Testable Reversible Adder with New Reversible Gate
21. FPGA Implementation of Low Power Parallel Multiplier
22. Compact Hardware Design of Whirlpool Hashing Core
23. A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction
24. A High Efficiency fully Digital Synchrouns Buck Converter Power Delivery System Based on Finite State Machine
25. X-Masking During Logic BIST and Its Impact on Defect Coverage
26. New techniques for untreatable fault identification in sequential circuits
27. New and Improved BIST Diagnosis Method from combinatorial group testing theory
28. Energy Management for battery powered Reconfigurable computing platforms
29. Design specific path delay testing in look up table based FPGA
30. Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison
31. Improving Linear Test Data Compression
32. Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction
33. Extraction Error Modeling and Automated Model Debugging in High-Performance Custom Designs

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