a) FPGA implementation
b) Implementation and prototyping on 8051 core architecture on FPGA
c) Implementation of 12C controller on FPGA
d) A VLSI Architecture For Visible Watermarking In A Secure Still Digital Camera (S2dc) Design (Corrected)
e) An FPGA-Based Architecture for Real Time Image Feature Extraction
f) A Low-Power Multiplier with the Spurious Power Suppression Technique
g) A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
h) Block-Based Multiperiod Dynamic Memory Design For Low Data Retention Pow ....etc

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kindly mail mini project topics along with the report n code for the above mentioned topic. THANK U ....etc

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1. The Design and FPGA Implementation of GF (2128 ) Multiplier for Ghash
2. Spread Spectrum Image Watermarking with Digital Design
3. FPGA Implementation of Viterbi Decoder IEEE 200
4. A Full Adder Based Methodology for the Design of Scaling Operation in Residue Number System IEEE 2008
5. Efficient On Chip Crosstalk Avoidance CODEC Design
6. Fault Secure Encoder and Decoder for Memory Applications
7. Hardware implementation of Variable Precision Multiplication on FPGA
8. A Fast Hardware Approach for Approximate, ....etc

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sir, i am pursuing my B.E. degree in electronics and telecommunication engineering and i am now in final year. i want to do project on VLSI technology but i am confused which project to choose.
so, i want you to sugest me a few topics regarding this.... ....etc

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Abstract— Computational Private Information Retrieval (cPIR) protocols allow a client to retrieve one bit from a database, without the server inferring any information about the queried bit. These protocols are too costly in practice because they invoke complex arithmetic operations for every bit of the database. In this paper, we present pCloud, a distributed system that constitutes the first attempt toward practical cPIR. Our approach assumes a disk-based architecture that retrieves one page with a single query. Using a striping technique, ....etc

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i need a helpstudent management system proposal ....etc

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1. High Speed DDR- SDRM Controller With 64-Bit Data Transfer
2. Redundant Radix “ 4 Co-Processor For High Speed Arithmetic Operations
3. Implementation Of PHELIX For Fast Encryption & Authentication
4. Design & Implementation Of ATM Knock Out Switch Using Concentrator
5. SDR “ SDRM Controller With 64 - Bit Data Transfer
6. Implementation Of Jpeg Base Line Image Compression
7. Implementation Of 8 “ Bit Pico Processor To Perform Arithmetic & Logical Operations
8. Design Of Ethernet IP Core 802.3 And Implementation
9. Im ....etc

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1. Design and implementation of client interface memory block for Double data rate synchronous dynamic random access memory – DDR SDRAM
2. Design and Implementation of RFID Mutual Authentication Protocol
3. FPGA Implementation of a Scalable Encryption Algorithm
4. VHDL implementation of Lossless Data Compression
5. Design of Secure Hash Algorithm-1 based on FPGA
6. Design and Implementation of Bluetooth security using VHDL
7. Design and implementation of Ethernet transmitter using VHDL
8. A Very Long Instruction Word Vector Media Copr ....etc

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1. A Novel Carry-Look ahead Approach to an Unified BCD and Binary Adder/ Subtractor
2. Speculative Carry Generation with Prefix Adder Using VHDL / Verilog
3. Improving Error Tolerance For Multithreaded Register Files
4. Higher Radix and Redundancy Factor for Floating Point Sort Division using VHDL/ Verilog
5. Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores using VHDL
6. Reconfigurable Architecture for Network Flow Analysis
7. The Reconfigurable Instruction Cell Array
8. System Architecture and ....etc

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1. FPGA Implementation Of Law Power Parallel Multiplier.
2. Designing Efficient Online Testable Reversible Adders With New Reversible Gate.
3. The Design And FPGA Implementation Of Gf(2A128) Multiplier For Ghash.
4. Bz-Fad: A Low-Power Low-Area Multiplier Based On Shift -And-Add Architecture.
5. A Fast Hardware Approach For Approximate, Efficient Logarithm And Antilogarithm Computations.
6. VLSI Design Of Diminished One Modulo 2n+1 Adder Using Circular Carry Selection.
7. A Full-Adder-Based Methodology For The Scaling Operation In Residue ....etc

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