1. FPGA Implementation Of Law Power Parallel Multiplier.
2. Designing Efficient Online Testable Reversible Adders With New Reversible Gate.
3. The Design And FPGA Implementation Of Gf(2A128) Multiplier For Ghash.
4. Bz-Fad: A Low-Power Low-Area Multiplier Based On Shift -And-Add Architecture.
5. A Fast Hardware Approach For Approximate, Efficient Logarithm And Antilogarithm Computations.
6. VLSI Design Of Diminished One Modulo 2n+1 Adder Using Circular Carry Selection.
7. A Full-Adder-Based Methodology For The Scaling Operation In Residue Number System.

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