Abstract
This paper describes the realization andcharacterisation of DTI (deep trench isolation)on thick (60μm) SOI (Silicon On Insulator)wafers for domestic and automotiveapplications . In this aim, DTI processoptimisation and adaptation permits to identifythe key parameters in breakdown voltagecapability. The role of different parts ofelaborated DTI was found to demonstrate thepossibility of good results in breakdownvoltage – up to 600V.
1. Introduction
BESOI (Bond and Etch SOI) substrates arecommonly used to reali ....etc

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ABSTRACT
This paper provides an introduction to silicon-on-insulator (SOI) technology and the operating principles of high-voltage SOI devices, reviews the performance of the available SOI switching devices in comparison with standard silicon devices, discusses the reasoning behind the use of SOI technology in power applications and covers the most advanced novel power SOI devices proposed to date. The impact of SOI technology on power integrated circuits (PICs) and the problems associated with the integration of high-voltag ....etc

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Abstract


A multidisciplinary team of end users and suppliers has collaborated to develop a novel yet broadly enabling process for the design, fabrication and assembly of Micro-Opto-Electro-Mechanical Systems (MOEMS). A key goal is to overcome the shortcomings of the polysilicon layer used for fabricating optical components in a conventional surface micromachining process. These shortcomings include the controllability and uniformity of material stress that is a major cause of curvature and deformation in released microstructures. The appr ....etc

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A SONOS memory cell is formed from a standard polysilicon NMOS transistor with the addition of a small sliver of silicon nitride inserted inside the transistor's gate oxide. The sliver of nitride is non-conductive but contains a large number of charge trapping sites able to hold an electrostatic charge. The nitride layer is electrically isolated from the surrounding transistor, although charges stored on the nitride directly affect the conductivity of the underlying transistor channel. The oxide/nitride sandwich typically consists of a 2 nm thi ....etc

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i need information about silicon on insulator. a need seminar report of it
send me the seminar report on silicon on insulator ....etc

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Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being ....etc

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i need seminar report /ppt on ultra thin body SOI. ....etc

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Abstract
Ultralow-power CMOSlSOI circuit technology that usesfully-depleted SO1 and multi-threshold (MT) CMOS circuitsmakes it possible to lower the supply voltage to 0.5 V andreduce the power dissipation of LSIs to I - 10 mW withoutany speed loss. We overview the ultralow-power CMOSlSOIcircuit technology and some ultralow-voltage LSIs based onMTCMOSlSOI circuits.IntroductionThe use of mobile systems with communication functionshas expanded rapidly in recent years. Considering the comingera of ubiquitous or pervasive networking computi ....etc

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pls send me some details about silicon on insulator implememtation for my seminars.... ....etc

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