05-05-2011, 04:15 PM
Abstract
Ultralow-power CMOSlSOI circuit technology that usesfully-depleted SO1 and multi-threshold (MT) CMOS circuitsmakes it possible to lower the supply voltage to 0.5 V andreduce the power dissipation of LSIs to I - 10 mW withoutany speed loss. We overview the ultralow-power CMOSlSOIcircuit technology and some ultralow-voltage LSIs based onMTCMOSlSOI circuits.IntroductionThe use of mobile systems with communication functionshas expanded rapidly in recent years. Considering the comingera of ubiquitous or pervasive networking computing, thenumber and variety of mobile units is expected to increasemuch more. For such equipment, further miniaturization andlonger battery life are required, and, eventually, battelylessmobile systems are foreseen. Ultralow-power design isessential for meeting these requirements. For CMOS LSIs,which are the key components of mobile systems, loweringsupply voltage and using SO1 devices are the most effectivedesign approaches for reducing power dissipation.MTCMOSlSOI circuits [I] [2] are suitable for operation atsupply voltages as low as 0.5 V. We have joined a nationalultralow-voltage SO1 project [3] whose aim is to expand theSO1 circuit technology to LSIs in mobile equipment. So far,some digital and analog components, such as a CPU, amemory, an analog/RF circuit, and a DC-DC converter for anultralow-power mobile system have been developed. Thisoverviews MTCMOSlSOI circuit technology and describesthe ultralow-voltage circuits.Ultralow-power Mobile SystemA block diagram of an ultralow-power mobile system isshown in Fig. 1. Applying 0.5-V digital LSIs and 0.5-I-Vanalog/RF LSIs, we set a power dissipation goal of about 1mW for the digital components and 10 mW for the analoglRFones. The relationship between the target application and LSIperformance is shown in Fig. 2. SO1 devices are already beingused in ultrahigh-speed and micro-watt applications likeservers and watches, but, not in wireless mobile equipmenilike PDAs. Their power dissipation is still over 100 mW.Our aim is to make the power dissipation about two orders ofmagnitude less than that of conventional LSIs.Key TechnologiesFor ultralow-power LSIs in mobile systems, the supplyvoltage must be lowered without degrading the operatingspeed. The threshold voltage of the MOSFETs must be6 0-7803-7310-3/02/$17.00200 02 IEEElowered at the same time to maintain the operating speed. Thepower dissipation of CMOS circuits mainly consists ofdynamic power dissipation for charging and discharging theoutput capacitance and static power dissipation due to asubthreshold leakage current. When supply voltage is reducedto I V, the dynamic power dissipation becomes the dominantfactor and the total power decreases in proportion to the squareof the supply voltage. But, when the supply voltage is lessthan I V, the threshold voltage of the MOSFETs must be setclose to 0 V. When this is done, the static power dissipationdue to the leakage current increases exponentially and the totalpower dissipation also increases. Hence, suppressing theleakagecurrent is the main issue in making ultralow-voltageLSIs.There are two key technologies for doing so. One is fullydepleted(FD) SO1 technology and the other is MTCMOScircuit technology [ I ] . The device structure of FD-MOSFETsis shown in Fig. 3(a):The silicon film is as thin as 50 nm orless, that is, its thickness is smaller than the surface depletionwidth of the MOSFETs. Since FD-MOSFETs have a steepsubthreshold swing close to the ideal value of 60 mV/&adeand are three terminal devices, they make it possible to reducethe threshold voltage without any leakage current. A triple-Vth MTCMOS circuit [2] is shown in Fig. 3(b). Themedium-Vth CMOS blocks are used for noncritical paths,thereby suppressing the leakage current in the active mode.And the high-Vth power-switch transistor reduces the leakagecurrent in the sleep mode.The energy-reduction effects [4] for each technology a ~ eshown in Fig. 4. Each energy dissipation is normalized to theminimum energy dissipation of the conventional CMOScircuit with the operating speed attainable at the supplyvoltage of I V and threshold voltage of 0.25 V. Figure 4shows that a single-Vth CMOSlSOI circuit composed of FDMOSFETscan reduce the energy dissipation 25 % from thatof the conventional CMOS circuit when the supply voltage isreduced from 1 V to 0.85 V. In addition, the multi-VthCMOSlSOI circuit with low- and medium-Vth MOSFETscan reduce the energy dissipation by more than 10 % fromthat of the single-Vth CMOS/SOI circuit when the supplyvoltage is reduced to 0.8 V. Moreover, at the supply voltageof 0.5 V, triple-Vth MTCMOS circuit can reduce the energydissipation by more than half that of the conventional CMOScircuit.
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