Abstract
This paper describes the realization andcharacterisation of DTI (deep trench isolation)on thick (60μm) SOI (Silicon On Insulator)wafers for domestic [1] and automotiveapplications [2]. In this aim, DTI processoptimisation and adaptation permits to identifythe key parameters in breakdown voltagecapability. The role of different parts ofelaborated DTI was found to demonstrate thepossibility of good results in breakdownvoltage – up to 600V.
1. Introduction
BESOI (Bond and Etch SOI) substrates arecommonly used to realise SOI power devicesintegration [3], [4], [5] because, thanks to theirBOx (Buried Oxide) they provide a good frontside / back side dielectric isolation. To achievea complete dielectric isolation, deep anisotropictrench realization [6] and filling is a keyprocess technique. In the first part of this paper,we describe deep trench etching and fillingprocess, in the second part we deal withelectrical characterisation and feed back onprocess and then conclude this paper.
2. Realization
For kW power applications, thick SOI activelayers are required in order to provide highcurrent section (low Ron at ON state), that isthe reason for 60μm SOI substrates choice. Forthis study, we use home made and SEH SOIsubstrates. A buried doped N+ layer wasrealised in the active silicon layer prior to thewafer bonding and etching, in order to createboth a buried electrode and isolation against theback potential. To provide a good contactbetween top surface and buried electrode, a twomask level trench process using heavily dopedtrench side walls was developed. Starting withoxidized wafers, the first step is a wet openingof large areas of thermal oxide prior to LPCVDoxide deposition in which deep trenches are drypatterned in oxide ICP Alcatel 601E tool was employed toprovide a multi-step high aspect ratio (AR=10,nominal width = 6μm) trenches etchingprocess. This etching process was monitored bya video camera and real time SOFIE End PointDetection (EPD) system, integrated to themachine. EPD system using an interferometricIR beam was optimised for the etch timeadjustment at each wafer, as a function ofSilicon TTV (Total Thickness Variation) andetching non uniformity. Complete trenchetching process includes three steps : starting ,main and finishing all automatically adjusted.The last etching step was particularly studiedLPCVD Oxide1st OxideSilicon substrate1st Trench2nd Trenchand adapted for a reproducible and smoothprofile. For this step, process adaptationconsists in plasma and gases conditionsadjustment. An example of SEM viewillustrates the bottom part of trench etched intwo different plasma conditions is given


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