Abstract
In this work, our goal is to develop a fast andaccurate power model of the ARM926EJ-S processorin the industrial design environment. Compared withexisting work on processor power modeling whichfocuses on the power states of processor core, ourmodel mostly focuses on the cache power model. Itgives more than 93% accuracy and 1600 times speedupcompared with post-layout gate-level power estimation.We also address two practical issues in applying theprocessor power model to the real design environment.One is to incorporate the power model into an existingcommercial instruction set simulator. The other is there-characterization of power model parameters to copewith different gate-level netlists of the processorobtained from different design teams and differentfabrication technology.Index Terms––Power estimation, processor, ARM926EJ-S, cache, sequential / non-sequential access, fillbuffer, instruction set simulator, re-characterization
I. Introduction
Embedded software design is getting more and moreattention as software (SW) complexity increases fasterthan hardware (HW) complexity [1]; thus, SW cost startsto dominate total chip design cost [2]. SW dominatespower consumption as well as system performance. Inparticular, handheld mobile devices (e.g., cell phone, PDA,PMP, and MP3 player) require SW running on the devicesto consume minimum power.Low power SW design technology covers a wide rangeof research area, e.g., instruction scheduling [10], dynamicvoltage scaling [11], and code transformation to reduceoff-chip memory accesses [12]. In reality, SW designersoften apply manual code optimization for bothperformance and power. Thus, the design space of lowpower SW is huge in terms of design technology and adhocmanual optimization.It is crucial to allow SW designers to explore the hugeSW design space to achieve low power design. To do that,we need accurate and fast methods of estimating the powerconsumption of SW running on the target processor.In this work, our goal is to develop a fast, but accuratepower model of the ARM926EJ-S processor in theindustrial design environment. The industrial designenvironment is different from the academic arena in twoaspects. First, designers often resort to commercialsimulators and tools. Thus, the power model needs to beincorporated into their existing simulators or tools.Second, there is a need to re-characterize the power modelparameters to deal with different gate-level netlists of theprocessor obtained from different design teams anddifferent fabrication technology1. In order to apply thepower model to a real design environment, we need toresolve these two issues.

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