21-01-2010, 11:07 PM
[attachment=1297]
ABSTRACT
This paper provides an introduction to silicon-on-insulator (SOI) technology and the operating principles of high-voltage SOI devices, reviews the performance of the available SOI switching devices in comparison with standard silicon devices, discusses the reasoning behind the use of SOI technology in power applications and covers the most advanced novel power SOI devices proposed to date. The impact of SOI technology on power integrated circuits (PICs) and the problems associated with the integration of high-voltage and low-voltage CMOS are also analyzed.
INTRODUCTION
SOI stands for silicon on insulator. This technology offers the possibility of building electronic devices in a thin layer of silicon that is electrically isolated from the thick semiconductor substrate through the use of a buried insulating layer. In the standard silicon technology the semiconductor substrate is associated with undesirable effects such as high leakage currents, parasitic bipolar components, and, more importantly, interference between individual active devices or circuits built in the same integrated chip. In addition, the use of SOI technology in CMOS (complementary metal oxide semiconductor) circuits may also shrink the dimensions of MOSFET (metal oxide semiconductor field effect transistor) devices and further push the frequency limit of silicon technology. The first confirmation that SOI technology is becoming the state-of the art technology in low-power ICâ„¢s came in 1999, when IBM launched the first fully functional SOI mainstream microprocessor. The IBM specifications predict a 25-35% improvement over similar bulk CMOS technology, which is equivalent to about two years of progress in bulk CMOS design and fabrication. Besides the fast speed, other benefits of the new SOI chip are reduced power consumption (up to 3 times) and a small soft error rate.
While SOI has already become a mature technology for low power CMOS circuits and justifiably represents the main manufacturing technology for the next generation of ULSI (Ultra Large Scale Integration) low power circuits, it is still an emerging technology for high voltage power integrated circuits. An increased effort is now directed towards developing advanced SOI power device structures for integrated circuits. Compared to bulk junction isolated (JI) devices, SOI devices and circuits offer improved isolation, reduced leakage currents and faster switching speed. Nevertheless, power devices made in SOI technology may suffer from reduced breakdown levels, self-heating effects and latch-up. Several solutions to address these drawbacks partially or totally have been proposed in this paper.
This paper gives an introduction to SOI technology and devices, reviews major steps in developing SOI power devices for integrated circuits, discusses advantages and drawbacks of SOI devices compared to bulk silicon devices and finally reveals the most recent developments in high voltage SOI structures.
SOI TECHNOLOGY
Creating defect free films of single crystal silicon on an insulating layer is a technological challenge. Several techniques have been developed to do this, but of these only a few have been commercially successful: silicon-on-sapphire (SOS), separation by implantation of oxygen (SIMOX), bonded and etched back SOI (BESOI) and uni-bond wafers produced by the smart cut process. Each of these in turn are discussed briefly:
Until the 1980™s silicon-on-sapphire was the Most mature of all SOI materials. It is produced by growing thin films of single crystal silicon on a sapphire wafer by chemical vapor deposition from silane gas at 1000°C. such films have the advantage of lying on a substrate which is extremely good conductor of heat; also they are highly immune to radiation. However, cost of silicon-on-sapphire material, the relatively poor quality of silicon films, and the emergence of new SOI technologies such as SIMOX and wafer bonding which are based purely on silicon have prevented it from becoming a mainstream SOI technology; its use remains a niche market.
Fig.1 The SIMOX manufacturing process
Although the concept of separation by implantation of oxygen (SIMOX) has been known since the 1970™s, it was only when a high current oxygen implanter became available in 1985 that SIMOX technology became a serious contender to SOS. To make SIMOX SOI wafers, a silicon substrate wafer is implanted with a high dose of oxygen ions at a high energy (1.8 x 1018 cm-2 at 150-200 Kev is typical) and is then annealed at 1300-1350°C for several hours; this is shown schematically in Fig.1. Under these conditions, the silicon layer and oxide layer is typically 200nm and 400 nm thick, respectively but with modern SIMOX process a top silicon layer as thin as 50nm and a buried oxide layer of thickness 100 nm are feasible.
Fig.2 The wafer bonding manufacturing process
Another modern technique for manufacturing SOI wafers is wafer bonding. The basic technique is shown in Fig.2 and relies on the fact that polished and flat wafers, when brought into contact at room temperature, are attached to each other by Van Der Waal™s forces and bond. To strengthen the ˜bond™ between the two wafers, a post bonding anneal at high temperature is usually performed and the top silicon wafer is then polished to create a thin silicon on insulator layer suitable for device manufacturing. However the uniformity can be improved by using wet-etches that are selective and will stop on a suitably placed etch stop layer of p¬+ silicon. Such techniques are known as bonded and etched-back SOI (BESOI).
Fig.3 The Smart-Cut manufacturing process
Alternatively, bonded wafers with silicon-on-insulator layers that are extremely uniform can be manufactured using the smart-cut method. This is shown in Fig.3. The device wafer, which has a layer of silicon dioxide on top of it, is implanted with a high dose of hydrogen ions (between 3.5 x 1016 and 1 x1017cm-2), after which it is bonded to the handle wafer which requires only a final high-temperature anneal and touch anneal and touch polish to yield the finished wafer. Versatility is the key advantage of the smart-cut method, as it can be used to create SOI wafers with buried oxide thickness from 200 nm to 4 nm, and silicon thickness from 200nm to 1.5µm12.
SOI LOW POWER DEVICES
Historically, the SOI technologies were developed as a solution to parasitic effects (such as the generation of a current by photo-ionization) noticed in thick substrates when a wafer was exposed to radiation. Today SOI technology is considered the most promising technology for monolithic integration of CMOS and bipolar devices. Besides immunizations from ionization by atoms and radiations the SOI technology provides several important advantages, such as reduced parasitic capacitances, short-channel effects, hot-carrier effects and static consumption. But the most important feature that establishes the SOI technology as a strong option for next generations of ULSI circuits is that it provides perfect isolation between individual device cells. Bulk circuits use reverse biased junctions to isolate individual devices from the substrate or /and from one another .for this reason the bulk technology in the high voltage field is commonly preferred to as junction isolation (JI) technology .the use of reverse biased junctions as isolation means has major drawbacks, such as increased parasitic capacitances and high leakage currents. Further more latch up structures such as npnp parasitic thyristors present in bulk CMOS inverters are completely eliminated in SOI technology. But there are still some problems associated with the SOI technique, such as floating substrate affects and self-heating, which will be addressed.
Fig.4 Cross-section through an SOI MOSFET structure
The basic structure of an SOI MOSFET is shown in Fig. 4; its basic operation is similar to the standard bulk MOSFET. When the gate source voltage is greater than the threshold voltage an inversion layer is formed at the surface, which allows transport of electrons from the source to the drain. The MOSFET can be turned of by lowering the gate voltage below the threshold voltage .the on state resistance of the MOSFET in the linear region is proportional to the length of the inversion layer and the thickness of the gate oxide and inversely eruptional to the difference between the gate voltage and the threshold voltage and the mobility in the inversion layer. When the drain voltage reaches a certain level, termed the saturation voltage, the condition for strong inversion is no longer satisfied and the inversion layer is pinched of at the drain side. This leads to current saturation .the main difference between SOI and bulk transistors is that the former is dually controlled by front and back gate bias. The two gates indices two depletion regions (fig 4) and, this gives rise to the following classification of SOI MOSFET structures (the indices 1 &2 stand for the front and back interface):
(a) Partially depleted, where d>xdmax1 + xdmax2 for any front and back gate bias.
(b) Partially or fully depleted, where it is possible to fully deplete si film only through the front and back gate:
max (xdmax1, xdmax2)<d< xdmax1 + xdmax2
© Fully depleted, when it is possible to totally deplete the si film through the effect of the front gate bias:
d<min (xmax1, xdmax2).
Among these the fully depleted devices feature the most attractive properties, such as high transconductance, mobility enhancement due to reduced surface field and improved sub threshold behavior (i.e. steep sub threshold slope). At the same time, the main parasitic capacitance in the SOI MOSFET comprising the gate oxide capacitance, the junction capacitance and the buried-oxide capacitance connected in series is limited y the buried “oxide capacitance an therefore for a relatively thick buried-oxide layer this capacitance can be made very small, one order of magnitude lower than that of an equivalent bulk MOSFET.
SOI POWER DEVICES
Some obvious benefits that SOI brings in low-power electronics, such as reduced short channel effects, the possibility of scaling down the channel and gate dimensions and the sharp sub-threshold gate voltage slope, are more or less unimportant aspects in power electronics. But the major advantage of SOI technology, the near ideal isolation, remains in place. Arguably, the isolation in power integrated circuits is even more stringent than in low-power circuits. This is because in JI technology the operation of power devices is often associated with the injection of carriers into silicon substrate, especially if such devices employ conductivity modulation to achieve a low on-state resistance. Parasitic collection of these injected carriers in the substrate by an adjacent large-area power device can cause it to turn-on, with potentially catastrophic consequences, such as power supply shorts. This has prevented the development of truly integrated power electronic circuits using junction isolation. With the advent of silicon-on insulator technology this limitation has been removed.
Isolation in SOI
Vertical isolation is provided by the buried oxide. Lateral isolation can be achieved by mesa etching and locos (local isolation of silicon) for thin SOI layers or, more commonly, by the formation of trench structures which are filled with oxide or with a combination of silicon oxide and polysilicon and which penetrate the silicon layer down to the buried oxide. The three techniques are shown in Fig.5
Fig.5 Isolation techniques in SOI high-voltage integrated circuits
SOI high-voltage structures
The two main high-voltage device structures, the LDMOSFET (lateral double diffused MOSFET) and the lateral insulate gate bipolar transistor (LIGBT), have made an impact in SOI technology, although other device structures, such as active trench gate devices, MOS-controllable thyristors and double-gate devices, have also been the object of intensive research.
Fig.6 SOI LDMOSFET cross-section
The basic SOI LDMOSFET structures is shown in Fig 6. When the voltage applied between the gate and source terminals is raised above the threshold potential, the device turns on and remains in the on state as long as the gate voltage is present. The channel formed between the n+ source and the n- drift layer allows transport of electrons from source to drain via the drift layer. The on-state resistance of the LDMOSFET is roughly given by the sum of the resistance of the channel and the resistance of the n- drift region. The presence of the buried oxide ensures vertical isolation and reduces the depletion volume, thus minimizing the leakage current in the off-state in the off state during the voltage blocking mode, the p+ well/n- drift layer junction is reverse biased and before the breakdown is reached the entire n- drift layer should be depleted.
Fig.7 SOI LIGBT cross-section
The SOI LIGBT known earlier as the SOICOMFET is shown in Fig 7.compared to the LDMOSFET, the LIGBT features an additional p+ layer at the anode side. When an electron channel is formed under the insulated gate and the anode junction becomes forward biased (i.e. the anode voltage rises above 0.6v) holes are injected into the n- drift layer from the p+ anode while at the other side electrons are injected into the n- drift region via the channel formed in the p well and the accumulation layer formed under the extension of the of the insulated gate in the n- drift layer. As in a PIN diode, the high “level injection of minority carriers into the drift region leads to accumulation of electrons and holes in this region and consequently a sharp increase in the conductivity of the top silicon layer.
Fig.8 On-state characteristics for Fig.9 Turn-off characteristics for 600V SOI LDMOSFET and LIGBT SOI LDMOSFET and LIGBT
The LIGBT has therefore a reduced on-state resistance compared to the LDMOSFET but at the expense of reduced switching speed due to the extra time needed for the removal of the excess charge.Fig .8 shows the I-V characteristics of an LDMOSFET and LIGBT of similar dimensions and voltage ratings. As expected the current in the LIGBT rises more sharply with the applied voltage; however, the turn-off time, and thus the associated switching losses, are higher in an LIGBT than in an LDMOSFET as can be seen in Fig .9.The buried oxide has an extra role in the IGBT, that of preventing carrier injection into the substrate. This is a very important advantage of the SOI LIGBT compared to its JI counterpart, where the injection of carriers deep into the substrate was the main cause for a very long turn-off tail. Another important advantage of SOI power devices is that they can work at higher environmental temperatures than bulk devices.
PROBLEMS WITH SOI POWER DEVICES
There are two main problems in soi devices. These are self-heating and low breakdown. The first is due to the oxide layer acting as a barrier, which prevents the heat from dissipating to the substrate. The thicker the oxide layer the more severe the self-heating is. The second problem is the lower breakdown voltage than on equivalent JI devices. This is due to a less effective RESURF effect. A thicker oxide increases the breakdown voltage but, as already mentioned, it also acts to enhance self-heating.
The RESURF effect in SOI power devices
The RESURF (reduced surface field) principle was introduced by Appels in 1980 for JI devices and extended for SOI devices by Huang and Baliga in 1991. It is a 2D effect based on the meeting of the depletion layers from the horizontal n- epi/p- substrate junction and the n- epi/p- well vertical junction.
Fig.10 (a) Lateral JI RESURF diode; (b) Lateral SOI RESURF diode
To explain the RESURF concept, consider a JI and an SOI diode as shown in Fig.10. For a JI diode, when the cathode voltage increases, the vertical depletion region expands in the substrate, while the horizontal one tends to expand from the anode into the drift region, to the cathode. These two depletion regions interfere such that the drift region becomes completely depleted at a lower voltage than that predicted by a 1D ideal junction. The substrate has a much smaller doping concentration than the epitaxial layer and therefore a large volume of the depletion region will expand in the thick p- substrate.
Fig.11 Potential contours in (a) conventional JI and SOI (b) SOI structure
For SOI devices on the other, the potential lines cannot expand in the substrate, since there is virtually no depletion region in the silicon substrate below the buried oxide (Fig .11). In this case the buried oxide layer supports a large fraction of the voltage across it. For thin SOI layers the buried oxide must be able to support the entire voltage across it. However the buried oxide does not help to redistribute the potential lines at the surface in the same way as in the case of the vertical p- substrate /n- drift junction in JI devices and thus the potential lines are not evenly distributed at the surface (Fig .11), resulting in a much lower breakdown voltage. A thicker oxide (e.g. 4µm) will alleviate this problem but still give poorer breakdown results compared to the JI case.
One solution proposed for this is to use a thin SOI film with a linearly graded doping profile. Another fundamental problem with SOI devices is a consequence of Gaussâ„¢ Law i.e. the conservation of electric field intensity, D, across materials with different dielectric constants.
Self-heating in SOI power devices
Compared to JI devices, SOI power devices suffer from severe self-heating due to presence of the buried oxide. Under prolonged high temperature operation, the stability of the device and the interconnects may degrade. In an SOI power device, the total device thermal resistance comprises the sum of the thermal resistances in the thin silicon layer (Si), the buried oxide layer, the substrate layer and the aluminium terminal (Al). For transient power overload conditions, a finite time is required for the temperature to reach its steady state level. The self-heating during large transient loads can result in very high temperatures, which may limit both the electrical operation of the power integrated circuit and its lifetime.
NOVEL SOI HIGH VOLTAGE DEVICE CONCEPTS
Novel SOI high voltage device structures have been recently proposed to overcome the drawbacks of standard SOI power devices mentioned above. Here we describe briefly the most promising solutions for the next generation of high voltage integrated circuits.
Ultra-thin SOI devices
As already mentioned, the first challenge for power SOI devices is to achieve a high breakdown voltage. In addition to the use of ultra thin SOI films to shorten the vertical impact ionization integration path, the structure uses a linearly graded doping concentration in the drift region to achieve a more uniform lateral electric field distribution along the drift region and so to optimize the RESURF condition. As shown in Fig.12,
Fig.12 An ultra-thin SOI LDMOSFET structure with a linearly doped drift layer
The doping concentration increases linearly in the drift region from the source end to the drain end. The structure also uses a gate extension in the form of a poly silicon layer extending over a large part of the field oxide above the drift region of the device. This induces an accumulation underneath the gate in the drift region, which further improves the specific ON resistance. A good compromise is found when the gate extends by a half of the drift length over the field oxide.
SIPOS devices
Another method to obtain amore uniform lateral electric field distribution along the drift region and increase the device breakdown voltage is to utilize semi insulating polycrystalline silicon (SIPOS) layers (Fig 13). Due to the material properties of SIPOS, the internal electric field is uniformly distributed along the drift region. The disadvantage of using a SIPOS layer is a decreased switching speed as a result of the extra resistance-capacitance charging paths.
Fig.13 an SOI LDMOSFET using a top SIPOS layer to enhance the breakdown Capability.
Partial SOI (PSOI) devices
Another method to alleviate the drawbacks of standard SOI high-voltage devices, while retaining one of the main advantages of the fabrication of power devices on SOI, namely the ability to integrate power devices alongside low-power CMOS on the same silicon substrate, is the use of a partial SOI substrate.
Fig.14 an LDMOSFET in partial silicon-on insulator
Fig .14 shows a cross-section of an LDMOSFET, which has been fabricated in ordinary silicon-on-insulator with one exception: the buried oxide has been patterned to leave a window beneath the drain of the LDMOSFET, which is completely filled with silicon. In this way, the voltage is supported across the depletion layer of the device/substrate junction as in a bulk Si PIC. Whereas in an ordinary SOI device the potential lines are constrained within the SOI layer and the buried oxide, as shown in Fig 11b, in the PSOI device the silicon window allows the potential lines to spread into the silicon substrate, as shown in Fig 15. Therefore the electric field is more uniform, and the potential distribution when the PSOI device is in the voltage-blocking mode resembles that of JI devices.
Fig.15 potential distribution during the voltage blocking mode in a partial SOI device
The other advantage of PSOI is a reduced self-heating effect. As already discussed, because silicon dioxide is not a good conductor of heat (its thermal conductivity is roughly one hundred times smaller than that of silicon), the buried oxide in an SOI LDMOSFET TRAPS generate heat within the SOI layer. However, in PSOI the silicon window allows heat to flow through to the substrate, thus reducing the self-heating and enlarging the safe operating area. Even though the use of PSOI devices is encouraging but the drawback is in manufacturing power devices and power integrated circuits in PSOI: the patterned buried oxide with silicon widows is complicated and expensive to manufacture.
3-D RESURF devices
Fig.16 an SOI 3-D RESURF diode
A very promising concept that is being pursued for future high-voltage devices is that of the 3D RESURF devices. The SOI 3D RESURF junction is shown in fig16. It comprises two PIN parallel junctions with drift regions of opposite doping brought together to form a third transverse junction. Since the width of the 3D junction is smaller than its length, the 3D junction depletes first transversally when a reverse voltage is applied between its terminals. The complete transverse depletion of the junction, at low reverse voltages, results in the p and n drift regions behaving virtually like a pure intrinsic layer, and thus independent of their actual n and p doping concentrations. If the 3D junction is incorporated into a MOSFET type device, the doping level in the individual n/p stripes which conduct current during the ˜on™ state of the MOSFET device can be increased well above the conventional doping limit associated with the breakdown voltage of a 1-sided p-n junction. This makes it possible, in principle, to have high-voltage LDMOS-type devices with on-state resistance as low as those achievable in conductivity-modulated power devices. The 3D devices are CMOS compatible and the SOI technology is well suited to achieve ideal isolation and low leakage currents. To achieve a high breakdown voltage (above 600v) and to avoid avalanche at the buried oxide/silicon interface, the thickness of the n-/p- layers has to be kept low- in the order of sub microns and the buried oxide has to have a thickness of at least 3µm.
SOI FOR POWER INTEGRATED CIRCUITS
Power integrated circuits (PICs) are defined as the monolithic integration of power devices with their controlling circuitry. The high input impedance, simple gate drive circuitry, fast switching and CMOS compatible drive levels have led to the rapid growth of PIC technology on recent years. JI technology on bulk PICs has many deficiencies, such as cross talk, latch-up, large-area isolation regions and high leakage currents, especially at high temperatures. As already mentioned, the full dielectric isolation provided by the SOI substrate offers effective isolation of control circuits from power output devices. It eliminates all DC current paths between adjacent devices with little electrical cross talk. In addition SOI technology enables high-temperature operation and allows a higher integration density. Fig 17 shows a PIC cell in SOI technology comprising a high voltage LDMOS and low-voltage CMOS device. The devices are usually fabricated on relatively thick films of silicon but recently there has been an increased interest in developing thin and ultra-thin film power devices because of their enhanced breakdown capability. One of the main uses of PICs is to assemble power conversion systems, which generally require a half-bride source-follower circuit to deliver power to the load.
Fig.17 a PIC cell in SOI technology with a high-voltage LDMOS and low-voltage MOSFET device integrated in the same chip
APPLICATIONS
SOI technology can be used for high-voltage and power ICs with various circuit topologies, including chopper circuits, push-pull circuits, half-bride and full-bride converters and inverters. Possible applications of these ICs include electronic lighting controls, flat display panels, high- precision power supplies, IC regulators, telecommunications, and some residential electronics (TV circuits, notebook computers, VCRs, etc.). However applications of SOI PICs in medium and high-power electronics will be limited until problems with breakdown capability and thermal management are properly addressed.
CONCLUSIONS
SOI has potential to be the future technology for high-voltage integrated circuits. Its near-ideal isolation, high integration density, reduced parasitic active components, low leakage currents, high operating frequency and CMOS compatibility makes it far more competitive than bulk technologies. The drawbacks of SOI power devices, such as limited breakdown capability, can be overcome by employing ultra-thin SOI films with linearly doped drift layers, SIPOS structures, partial SOI substrates and 3D RESURF devices. However, with the exception of partial SOI structures, self-heating remain a problem to be addressed. This limits the power-handling capability of these devices and may affect the reliability of the entire circuit. Nevertheless recent efforts in this direction have led to the development of commercial power integrated circuits on SOI substrates with voltage ratings up to 650V and power ratings up to 50W.
BIBILIOGRAPHY
REFERENCE BOOKS AND MAGAZINES
ËœELECTRONICS & COMMUNICATION ENGINEERING JOURNALâ„¢ (FEB, 2000)
ËœHIGH VOLTAGE SOI FOR SINGLE-CHIP POWERâ„¢ (SEMICONDUCTOR DEVICES), JUNE1999.
˜CMOS “CIRCUIT DESIGN, LAYOUT & SIMULATION™ (JACOB BAKER R., LI H.W&BOYCE D.E)
WEBSITES BROUSED
WWW.IEEE.ORG
WWW.SOI SUBSTRATE HOME.COM
CONTENTS
INTRODUCTION
SOI TECHNOLOGY
SOI LOW-POWER DEVICES
SOI POWER DEVICES
Isolation in SOI
SOI high-voltage structures
PROBLEMS WITH SOI POWER DEVICES
The RESURF effect in SOI power devices
Self-heating in SOI power devices
NOVEL SOI HIGH VOLTAGE DEVICE CONCEPTS
Ultra-thin SOI devices
SIPOS devices
Partial SOI (PSOI) devices
3-D RESURF devices
SOI FOR POWER INTEGRATED CIRCUITS
CONCLUSIONS
BIBILIOGRAPHY
ACKNOWLEDGEMENT
I extend my sincere thanks to Prof. P.V.Abdul Hameed, Head of the Department, Electronics and Communication Engineering, for providing me his invaluable guidance for the Seminar.
I express my sincere gratitude to my Seminar Coordinator and Staff in Charge Mr. Manoj K, for his cooperation and guidance in the preparation and presentation of this seminars.
I also extend my sincere thanks to all the faculty members of Electronics and Communication Department for their support and encouragement.
Shabeer Kunhi Mohamed
