SiGe HBT Technology: A New Contender
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SiGe HBT Technology: A New Contender

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II. SiGe HBT TECHNOLOGY
In order to provide a logical framework for this paper, the
experimental results presented will be largely from IBM’s
SiGe HBT technology [25]. This technology is representative
of the state-of-the-art in 1998, is currently qualified and in
commercial production on 200-mm wafers in an advanced
CMOS fabrication facility, and is thus arguably the most
“real” SiGe HBT technology worldwide. The basic tenets
which dictate the final implementation of IBM’s SiGe HBT
technology are: 1) maintain strict processing compatibility
with existing CMOS tool sets and metallization schemes


THE SiGe HBT
This section gives an overview of the performance
capabilities of state-of-the-art SiGe HBT’s. Basic device
physics, dc and ac performance advantages over Si BJT’s,
low-frequency and broad-band noise characteristics, radiation
tolerance, temperature effects, and reliability issues are
addressed. For brevity, only the final results of the basic
device physics derivations are included. The interested reader
is referred to [58] for more complete derivations.

DC Characteristics
The dc consequences of introducing Ge into the base region
of an SiGe HBT can best be understood by considering an
energy-band diagram of the resultant device and comparing
it to Si. As shown in Fig. 5 by the dashed line, the Ge is
compositionally graded from low concentration at the EB
junction to high concentration at the collector–base (CB)
junction.


V. STATUS AND FUTURE DIRECTIONS
In the ten-and-one-half short years since the first demonstration
of a functional device, SiGe technology has emerged
from the research lab and entered manufacturing. In this final
section, state-of-the-art circuits are reviewed, followed by a
brief look at fundamental device limits and future directions


VI. CONCLUSION
It has been argued throughout this paper that SiGe is an
idea whose time has come. The original motivation for developing
SiGe technology is beautifully simple: let us combine
transistor performance which is competitive with the III–V
technologies with the processing maturity, integration levels,
yield, and, hence, cost commonly associated with conventional
Si fabrication. What once seemed like a dream is now reality
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