Modeling and Fabrication of Vertical Pillar MOSFETs Made in
Recrystallized Si

[attachment=16457]

INTRODUCTION
Vertical pillar MOSFETs fabricated in recrystallized silicon
have shown the benefits of designing high density DRAMS [2] [3].
However, these devices have traps in the channel originating
from dislocations and stacking faults [l]. These traps affect
the charge profile in the device causing unpredictable electrical
characteristics. Therefore it is necessary to establish an analytical
model to understand the effects of bulk traps on the
device characteristics of surrounding gate MOSFETs. In this
paper, simple formulas for threshold voltage of a vertical pillar
MOSFET with bulk traps are presented. The model is used to
extract the defect density of fabricated devices.


MEASURED DEVICE CHARACTERISTICS
The fabrication procedure for the experimental devices was
reported in 111. Fig. 5 shows a SEh4 image after the gatc spacer
etch. The channel length is 0.8 pm and the gate oxide thickness
is 18 nm with a channel concentration of 2 x 1017cm-". Measured
electrical data from devices shows that the threshold voltage
is distributed between 0.85 V and 1.32 V as shown in Fig. G.
The wide distribution of Vth is attributed to two main causes


CONCLUSION
We have developed a simple analytical model for a vertical
pillar MOSFET when uniformly distributed bulk traps are presented.
The model shows an increase in threshold voltage as tlic
density of the bulk traps is increased, independent of the depletion
codition. The electrical characteristics of fabricated devices
show good performance indicating a small number of defects in
the channel. Therefore this device is a promising candidate for
3-D integration and for memory cell structures.