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Abstract
In view of changing the type of energy conversion inCMOS circuits, this paper investigates low power CMOScircuit design which adopts gradually changing powerclock. First, we discuss the algebraic expressions and thecorresponding properties of clocked power signals, then aclocked CMOS gate structure is presented. The PSPICEsimulations demonstrate the low power characteristic ofclocked CMOS circuits using trapezoidal power-clock.Finally, this paper also explores the design of sequentialcircuit, which adopts flip-flop with clocke ....etc

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Title: Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
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Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

Hamid Mahmoodi, Member, IEEE, Vishy Tirumalashetty, Matthew Cooke, and Kaushik Roy, Fellow, IEEE


Abstract—
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant en ....etc

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