10-03-2017, 02:56 PM
The Manchester Carry-Chain Adder is a chain of step transistors that are used to implement the transport chain. During preload, all intermediate nodes (eg, Cout0) are loaded to Vdd. During the evaluation phase, Cout_k is discharged if there is an incoming Cin0 receiver and the above propagation signals (P0 ... Pk-1) are high. Only 4 diffusion capacitances are present at each node, but the distributed RC-nature of the string results in a delay that is quadratic with the number of bits. The sizing of the transistor was performed to improve the performance. Details are detailed in the design strategy section.
The Manchester carry chain was designed using dynamic logic and implements the following logical function:
Coi = Gi + PiCoi-1
Where Co is the carry out.
Design strategy
The good thing about Manchester Carry Chains is that there is no door between the stages. There are only 4 broadcast capabilities at each node. The bad news is that the number of transistors in series increases with the nubmer of stages (the critical path involves a propagation transistor in series for each bit); So the delay will grow as n2. The delay in the worst case depends on the generation of propagation propagation signals. The transistors were sized as follows to improve performance: Consider the delay in the worst case of the next transport chain: Elmore delay is given by. Therefore, the delay is tp = 0.69 (R1 + R2 + R3 + R4 + C4 + (R1 + R2) R5) C5 When R6 appears 6 times in the expression, it makes sense to minimize this first. When we reduce R by a factor of k, the capacitance in each stage increases by a value of (a), (R + R + R + Of k and the area is increased. Ak = 1.5, the area increases by 3.5 times BUT delay is reduced by 40%. This is a perfect example of the compensation between speed and area. The size of the transistor Was designed in such a way that the resistance of each The consecutive transistor in the chain was slightly higher than the last to minimize the delay (by a factor of 1.5 - reduction delay by 40% calculated using Elmore delay ) The hoisting transistors were similarly sized to provide appropriate resistance to their respective deployable transistors.
The Manchester carry chain was designed using dynamic logic and implements the following logical function:
Coi = Gi + PiCoi-1
Where Co is the carry out.
Design strategy
The good thing about Manchester Carry Chains is that there is no door between the stages. There are only 4 broadcast capabilities at each node. The bad news is that the number of transistors in series increases with the nubmer of stages (the critical path involves a propagation transistor in series for each bit); So the delay will grow as n2. The delay in the worst case depends on the generation of propagation propagation signals. The transistors were sized as follows to improve performance: Consider the delay in the worst case of the next transport chain: Elmore delay is given by. Therefore, the delay is tp = 0.69 (R1 + R2 + R3 + R4 + C4 + (R1 + R2) R5) C5 When R6 appears 6 times in the expression, it makes sense to minimize this first. When we reduce R by a factor of k, the capacitance in each stage increases by a value of (a), (R + R + R + Of k and the area is increased. Ak = 1.5, the area increases by 3.5 times BUT delay is reduced by 40%. This is a perfect example of the compensation between speed and area. The size of the transistor Was designed in such a way that the resistance of each The consecutive transistor in the chain was slightly higher than the last to minimize the delay (by a factor of 1.5 - reduction delay by 40% calculated using Elmore delay ) The hoisting transistors were similarly sized to provide appropriate resistance to their respective deployable transistors.