04-12-2014, 10:56 PM
Please I need help on how to go about building a testbench for hamming code generator in VHDL. Thank you
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vhdl test bench for hamming code generator
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Please I need help on how to go about building a testbench for hamming code generator in VHDL. Thank you
31-03-2017, 12:28 PM
The Hamming code is useful in error correction in the linear lock code. This code will encode four data bits and generate seven code bits by adding three bits as parity bits. It was introduced by Richard W. Hamming. This algorithm can detect one- and two-bit errors and can correct a bit error. Given below the code will generate (7.4) Systematic Hamming Encoder. This encoder will use 4 less significant bits as data inputs and most 3 significant bits as parity bits.
The equations of the parity bits are given below
P0 = datain (0) xor datain (1) xor datain (3)
P1 = datain (0) xor datain (2) xor datain (3)
P2 = datain (1) xor datain (2) xor datain (3)
The equations of the parity bits are given below
P0 = datain (0) xor datain (1) xor datain (3)
P1 = datain (0) xor datain (2) xor datain (3)
P2 = datain (1) xor datain (2) xor datain (3)
Quote:library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY hamming_encoder IS
PORT(datain : IN BIT_VECTOR(0 TO 3); --d0 d1 d2 d3
hamout : OUT BIT_VECTOR(0 TO 6)); --d0 d1 d2 d3 p0 p1 p2
END hamming_encoder;
ARCHITECTURE beh OF hamming_encoder IS
SIGNAL p0, p1, p2 : BIT; --check bits
BEGIN
--generate check bits
p0 <= (datain(0) XOR datain(1)) XOR datain(3);
p1 <= (datain(0) XOR datain(2)) XOR datain(3);
p2 <= (datain(1) XOR datain(2)) XOR datain(3);
--connect up outputs
hamout(4 TO 6) <= (p0, p1, p2);
hamout(0 TO 3) <= datain(0 TO 3);
END beh;
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