18-12-2014, 10:00 PM
vhdl code for 128 bit carry select adder
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vhdl code for 128 bit carry select adder
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vhdl code for 128 bit carry select adder
15-04-2017, 12:19 PM
In many data processing processors Carry Select Adder (CSLA) is one of the fastest adder used to perform arithmetic functions. The next technologies show that there is scope for reducing area and energy consumption in the CSLA. This work uses a simple modification of the door level to significantly reduce the area and energy of the CSLA. Based on this modification, the CSLA architecture has been developed and can be compared with the regular CSLA architecture. The proposed design has reduced area and power compared to the regular CSLA with only a slight increase in delay. This work evaluates the performance of the proposed designs in terms of delay, area, power and their products by hand with logical effort and by custom design and design in 0.18 m CMOS process technology.
The area and power reduction in the data path logic systems are the main area of research in the design of VLSI systems. The addition and multiplication of high speed has always been a fundamental requirement of the processors and systems of high performance. In digital adders, the rate of addition is limited by the time required to propagate a charge through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been added and a carry has been propagated to the next position. The greatest speed limitation in any adder is in the production of carries and many authors have considered the problem of addition. The CSLA is used in many computer systems to moderate the problem of transport propagation delay by independently generating multiple hauls and then selecting a haul to generate the sum. However, the CSLA is not efficient in the area because it uses multiple Ripper Carry Adders (RCA) pairs to generate the partial sum and carry it by considering the carry input and then the final sum and carry are selected by the multiplexers (mux) . To overcome the above problem, the basic idea of the proposed work is by using binary nbit to the excess-1 code converters (BEC) to improve the rate of addition. This logic can be implemented with any type of adder to further improve speed. Use Binary Converter to Excess -1 (BEC) instead of RCA in the regular CSLA to achieve a lower consumption of area and power. The main advantage of this BEC logic comes from the smaller number of logic gates than the Full Adder (FA) structure.
The area and power reduction in the data path logic systems are the main area of research in the design of VLSI systems. The addition and multiplication of high speed has always been a fundamental requirement of the processors and systems of high performance. In digital adders, the rate of addition is limited by the time required to propagate a charge through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been added and a carry has been propagated to the next position. The greatest speed limitation in any adder is in the production of carries and many authors have considered the problem of addition. The CSLA is used in many computer systems to moderate the problem of transport propagation delay by independently generating multiple hauls and then selecting a haul to generate the sum. However, the CSLA is not efficient in the area because it uses multiple Ripper Carry Adders (RCA) pairs to generate the partial sum and carry it by considering the carry input and then the final sum and carry are selected by the multiplexers (mux) . To overcome the above problem, the basic idea of the proposed work is by using binary nbit to the excess-1 code converters (BEC) to improve the rate of addition. This logic can be implemented with any type of adder to further improve speed. Use Binary Converter to Excess -1 (BEC) instead of RCA in the regular CSLA to achieve a lower consumption of area and power. The main advantage of this BEC logic comes from the smaller number of logic gates than the Full Adder (FA) structure.
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