24-02-2015, 09:57 AM
i want error vhdl code for error tolerant adder ..
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vhdl code for error tolerant adder
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i want error vhdl code for error tolerant adder ..
09-03-2017, 11:43 AM
In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test Error Tolerance (ET) is a new Error Tolerant Additive (ETA) is proposed. The ETA is able to alleviate strict restriction on accuracy while at the same time achieving huge improvements in power consumption and speed performance. Compared with its conventional counterparts, the proposed ETA is able to achieve improvements in the Power-Delay (PDP) product. Conclusion / Recommendations: An important potential application of the proposed ETA is in digital signal processing systems that can tolerate a number of errors. The delay and power are compared for several summers like RCA and CLA. It is found that ETA has high speed and less power compared to its counterparts.
In conventional digital VLSI design is generally assumed that a usable circuit / system should always provide accurate and accurate results. But, in fact, such perfect operations are seldom necessary in our mundane non-digital experiences. The world accepts "analog computing", which produces "good enough" results rather than totally accurate results (Breuer, 2005). Data processed by many digital systems may already contain errors. In many applications, such as a communication system, the analog signal from the outside world must first be sampled before being converted into digital data. The digital data is then processed and transmitted in a noisy channel before being converted back to an analog signal. During this process, errors can occur anywhere. In addition, due to advances in the transistor size scale, factors such as noise and process variations that were previously insignificant are becoming important in today's International Technology Road map for Semiconductors IC design. Based on the VLSI digital design feature, some novel concepts and design techniques have been proposed. The concept of Tolerance to Error (ET) (Breuer and Zhu, 2006, Breuer et al., 2004, Breuer, 2004, Lee and others, 2005, Chong and Ortega, 2005, Chung and Ortega, 2005, Kuok, 1995, Hsieh Et And the PCMOS technology (Palem, 2005; Cheemalavagu et al., 2004; Korkmaz et al., 2006) are two of them.
According to the definition, a circuit is error tolerant if:
(1) contains defects that cause internal errors and may cause external errors and
(2) the system incorporating this circuit produces acceptable results.
The "imperfect" attribute does not seem attractive. However, the need for a fault tolerant circuit (Breuer and Zhu, 2006, Breuer et al., 2004, Breuer, 2004, Lee et al., 2005, Chong and Ortega, 2005, Chung and Ortega, 2005, Kuok, 1995; Hsieh et al., 2007) was predicted in the 2003 International Technology Roadmap for Semiconductors (ITRS) International Semiconductor Technology Roadmap. To address erroneous problems, some truncated aggregators / multipliers have been reported (Stine et al. 2005, Van and Yang, 2005) but are not able to function well in their speed, power, area or accuracy. The "tagged prefixed aggregator" (Stine et al., 2005) works better than the non flagged version with a speed increase of 1.3% but at the expense of the extra 2% area of silicon. As for "fixed-width multipliers efficient in the area of low error" (Van and Yang, 2005), it can have an area improvement of 46.67% but has an average error of 12.4%. Of course, not all digital systems can tolerate errors. In digital systems such as control systems, the correction of the output signal is extremely important and this negates the use of the fault-tolerant circuit.
In conventional digital VLSI design is generally assumed that a usable circuit / system should always provide accurate and accurate results. But, in fact, such perfect operations are seldom necessary in our mundane non-digital experiences. The world accepts "analog computing", which produces "good enough" results rather than totally accurate results (Breuer, 2005). Data processed by many digital systems may already contain errors. In many applications, such as a communication system, the analog signal from the outside world must first be sampled before being converted into digital data. The digital data is then processed and transmitted in a noisy channel before being converted back to an analog signal. During this process, errors can occur anywhere. In addition, due to advances in the transistor size scale, factors such as noise and process variations that were previously insignificant are becoming important in today's International Technology Road map for Semiconductors IC design. Based on the VLSI digital design feature, some novel concepts and design techniques have been proposed. The concept of Tolerance to Error (ET) (Breuer and Zhu, 2006, Breuer et al., 2004, Breuer, 2004, Lee and others, 2005, Chong and Ortega, 2005, Chung and Ortega, 2005, Kuok, 1995, Hsieh Et And the PCMOS technology (Palem, 2005; Cheemalavagu et al., 2004; Korkmaz et al., 2006) are two of them.
According to the definition, a circuit is error tolerant if:
(1) contains defects that cause internal errors and may cause external errors and
(2) the system incorporating this circuit produces acceptable results.
The "imperfect" attribute does not seem attractive. However, the need for a fault tolerant circuit (Breuer and Zhu, 2006, Breuer et al., 2004, Breuer, 2004, Lee et al., 2005, Chong and Ortega, 2005, Chung and Ortega, 2005, Kuok, 1995; Hsieh et al., 2007) was predicted in the 2003 International Technology Roadmap for Semiconductors (ITRS) International Semiconductor Technology Roadmap. To address erroneous problems, some truncated aggregators / multipliers have been reported (Stine et al. 2005, Van and Yang, 2005) but are not able to function well in their speed, power, area or accuracy. The "tagged prefixed aggregator" (Stine et al., 2005) works better than the non flagged version with a speed increase of 1.3% but at the expense of the extra 2% area of silicon. As for "fixed-width multipliers efficient in the area of low error" (Van and Yang, 2005), it can have an area improvement of 46.67% but has an average error of 12.4%. Of course, not all digital systems can tolerate errors. In digital systems such as control systems, the correction of the output signal is extremely important and this negates the use of the fault-tolerant circuit.
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