31-03-2017, 04:16 PM
The multiplier is an important block in most digital and high-performance systems. Therefore, the performance of such a system can be improved by implementing a high-speed multiplier. Varieties of multipliers are available, in which a fast multiplier-based coded Wallace tree is discussed in this research. The conventional Wallace tree multiplier is based on carry save adder. Here the speed of the multiplier is improved by introducing compressors instead of the transport saving adder. Compressor 3-2, compressor 4-2, compressors 5-2 and compressors 7-2 are used with the Wallace tree multiplier. The higher order compressors have a better performance compared to the compressor 3-2. Thus, the speed of the multiplier can be improved by introducing the higher order compressors. The coding is performed in Verilog HDL and the synthesis is performed using Xilinx ISE 14.7. Further analysis is done using the Cadence Encounter tool. Several design parameters such as delay, area, power of the Wallace booth multiplier with various compressors and different radix are analyzed.
Numerous multiplier architectures have been published in the literature during the last decades. The multiplier is one of the key hardware blocks in most digital and high-performance systems, such as digital signal processors and microprocessors. With recent advances in technology, many researchers have worked on the design of increasingly efficient multipliers. Its aim is to provide greater speed and lower power consumption even while occupying a reduced area of silicon. This makes them compatible for various implementations of complex and portable VLSI circuits. However, the fact is that area and speed are two conflicting performance constraints. Therefore, increased speed innovation always results in a larger area. In this article, we come to a better balance between the two, by performing a slightly increased speed performance through a small increase in the number of transistors. The new architecture improves the speed performance of the widely recognized Wallace tree multiplier. The structural optimization is performed on the conventional Wallace multiplier, in such a way that the latency of the total circuit is considerably reduced. Wallace's tree basically multiplies two unsigned integers.
Numerous multiplier architectures have been published in the literature during the last decades. The multiplier is one of the key hardware blocks in most digital and high-performance systems, such as digital signal processors and microprocessors. With recent advances in technology, many researchers have worked on the design of increasingly efficient multipliers. Its aim is to provide greater speed and lower power consumption even while occupying a reduced area of silicon. This makes them compatible for various implementations of complex and portable VLSI circuits. However, the fact is that area and speed are two conflicting performance constraints. Therefore, increased speed innovation always results in a larger area. In this article, we come to a better balance between the two, by performing a slightly increased speed performance through a small increase in the number of transistors. The new architecture improves the speed performance of the widely recognized Wallace tree multiplier. The structural optimization is performed on the conventional Wallace multiplier, in such a way that the latency of the total circuit is considerably reduced. Wallace's tree basically multiplies two unsigned integers.
