28-03-2011, 10:24 AM
[attachment=11126]
STUDY OF SIMULATION USING VERILOG MODULE
AIM:
To study the simulation process using XILINX ISE 9.Li tool
THEORY:
The Simulator environment must maintain information about various design units involved in simulation such as location of libraries . If the verilog HDL analyzer returns errors relating to the absence of key libraries it is most likely a result of the lack of definition of the physical location of the logical libraries.
PROCEDURE
Intialize the Xilinx ISE 9.li simulator by double clicking the icon on the desktop.
In the design summary window go to New project through the File menu.
Enter the Project Name In the New project wizard and then click Next.
In the New project wizard select the following specifications.
Project category ALL
Family spartan2 (select required family)
Device XC2S150(select required device)
Package PQ208 (select required package)
Speed -6
Top level source type HDL
System tool XST(VHDL/Verilog)
Program language Verilog (select required language)
After selecting the required specifications click Next and select New source.
In the New source wizard select Verilog module and enter the File name and then click Next.
Set the input and output variable to be used and then click Next
The Summary of the New source wizard is displayed ,conform the displayed details by clicking finish icon.
Then click Next consecutively until the coding screen appears
Enter the project coding in the appropriate place.
Then go to the Synthesis XST and double click the check syntax . It checks for error and displays the result.
Go to the source and select synthesis /implementation .Here right click the mouse and select New Source
