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Abstract:
OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers and sent simultaneously in time. The result is an optimum usage of bandwidth. A set of orthogonal sub-carriers together forms an OFDM symbol. To avoid ISI due to multi-path, successive OFDM symbols are separated by guard band. This makes the OFDM system resistant to multi-path effects. Although OFDM in theory has been in existence for a long time, recent developments in DSP and VLSI technologies have made it a feasible option. This paper describes the VLSI implementation of OFDM in details. Specifically the 802.11a OFDM system has been considered in this paper. However, the same considerations would be helpful in implementing any OFDM system in VLSI.OFDM is fast gaining popularity in broadband standards and high-speed wireless LAN.
1. Introduction
OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers. Unlike single carrier systems, all the frequencies are sent simultaneously in time. OFDM offers several advantages over single carrier system like better multi-path effect immunity, simpler channel equalization and relaxed timing acquisition constraints. But it is more susceptible to local frequency offset and radio front-end non-linearities.
The frequencies used in OFDM system are orthogonal. Neighboring frequencies with overlapping spectrum can therefore be used. This property is shown in the figure where f1, f2 and f3 orthogonal. This results in efficient usage of BW. The OFDM is therefore able to provide higher data rate for the same BW.
2. OFDM Transceiver
Each sub-carrier in an OFDM system is modulated in amplitude and phase by the data bits. Depending on the kind of modulation technique used one or more bits are used to modulate each sub-carrier. Modulation techniques typically used are BPSK, QPSK, 16QAM, 64QAM etc. The process of combining different sub-carriers to form a composite time-domain signal is achieved using Fast Fourier transform. Different coding schemes like block coding, convolutional coding or both is used to achieve better performance in low SNR conditions. Interleaving is done which involves assigning adjacent data bits to non-adjacent bits to avoid burst errors under highly selective fading.
In the approach shown in Figure the entire functionality is implemented in hardware. Following are the advantages of this approach:
• Lower gate count compared to DSP+RAM+ROM, hence lower cost
• Low power consumption
Due to the advantages mentioned above a VLSI based approach was considered for implementation of an 802.11a Base band. Following sections describe the VLSI based implementation in details.
4. Design Methodology
Early in the development cycle, different communication and signal processing algorithms are evaluated for their performance under different conditions like noise, multipath channel and radio non-linearity. Since most of these algorithms are coded in "C" or tools like Matlab, it is important to have a verification mechanism which ensures that the hardware implementation (RTL) is same as the "C" implementation of the algorithm. The flow is shown in the Figure.
5.1 Specifications of the OFDM transceiver
• Data rates to be supported
• Range and multipath tolerance
• Indoor/Outdoor applications
• Multi-mode: 802.11a only or 802.11a+HiperLAN/2
5.2 Design trade-offs
• Area - Smaller the die size lesser the chip cost
• Power - Low power crucial for battery operated mobile devices
• Ease of implementation - Easy to debug and maintain
• Customizability - Should be customizable to future standards with variations in OFDM parameters
6. Algorithm survey & simulation
The simulation at algorithmic level is to determine performance of algorithms for various non-linearities and imperfections. The algorithms are tweaked and fine tuned to get the required performance. The following algorithms/parameters are verified
• Channel estimation and compensation for different channel models (Rayleigh, Rician, JTC, Two ray) for different delay spreads
• Correlator performance for different delay spreads and different SNR
• Frequency estimation algorithm for different SNR and frequency offsets
• Compensation for Phase noise and error in Frequency offset estimation
• System tolerance for I/Q phase and amplitude imbalance
• FFT simulation to determine the optimum fixed-point widths
• Wave shaping filter to get the desired spectrum mask
• Viterbi BER performance for different SNR and traceback length
• Determine clipping levels for efficient PA use
• Effect of ADC/DAC width on the EVM and optimum ADC/DAC width
• Receive AGC
6.1 Fixed point simulation
One of the decisions to be taken early in the design cycle is the format or representation of data. Floating point implementation results in higher hardware costs and additional circuits related with normalizing of numbers. Floating point representation is useful when dealing with data of different ranges. But this however is not true as the Baseband circuits have a fair idea of the range of values they will work on. So a fixed-point representation will be more efficient. Further in fixed point a choice can be made between signed and 2's complement representation.
The width of representation need not be constant throughout the Baseband and it depends on the accuracy needed at different points in transmit or receive path. A small change in the number of bits in the representation could result in a significant change in the size of arithmetic circuits especially multipliers.
Shown below is the loss of SNR because of decrease in the width of representation.
6.2 Simulation setup
The algorithms could be simulated in a variety of tools/languages like SPW, MATLAB, "C" or a mix of these. SPW has an exhaustive floating point and fixed-point library. SPW also provides feature to plug-in RTL modules and do a co-simulation of SPW system and Verilog. This helps in verifying the RTL implementation of algorithms against the SPW/C implementation.