25-01-2012, 04:42 PM
Low-Power Multiplier Design with Row and Column Bypassing
[attachment=16610]
INTRODUCTION
Multiplication[1] is an essential arithmetic operation in
DSP applications. For the multiplication of two unsigned
n-bit numbers, the multiplicand A = an-1 an-2, . . . , a0 and
the multiplier B = bn-1 bn-2, . . . , b0, the product P = P2n-
1P2n-2, . . . , P0, can be represented as the following
equation:
LOW-POWER MULTIPLIER WITH ROW OR
COLUMN BYPASSING
For a low-power row-bypassing multiplier[7], the
addition operations in the j-th row can be disabled to
reduce the power dissipation if the bit bj in the multiplier
is 0, i. e., all partial products aibj, 0≤ i ≤ n-1, are zero. As
a result, the addition operations in the j-th row of CSAs in
Fig. 1 can be bypassed and the outputs from the (j-1)-th
row of CSAs can be directly fed to the (j+1)-th row of
CSAs without affecting the multiplication result.
LOW-POWER MULTIPLIER WITH ROW AND
COLUMN BYPASSING
According to the bypassing features in the previous
low-power multipliers, the addition operations in the
(i+1)-th column or the j-th row can be bypassed for the
power reduction if the bit, ai, in the multiplicand is 0 or
the bit, bj, in the multiplier is 0. On the other hand, the
extra correcting circuits in the row-bypassing multiplier
are applied to add the bypassed carry results into the
multiplication result.
CONCLUSIONS
Based on the simplification of the incremental adders
and half adders instead of full adders in an array
multiplier, a low-power multiplier design with row and
column bypassing is proposed. Compared with the rowbypassing
or column-bypassing multipliers, the
experimental results show that our proposed low-power
multiplier achieves higher power reduction with lower
hardware overhead.
