[attachment=2590]


AUTOMATIC SPEED CONTROLLER FOR FANS WITH ON/OFF CONTROL BY LIGHT

ABSTRACT
The circuit designed here lets us turn ON/OFF a fan or any device by just directing a torch light or any other light towards its light-dependent resistor. In short we are tiying to develop a remote control for turning ON/OFF an electronic device.
During summer nights, the temperature is initially quite high. As time passes, the temperature starts dropping. Also, after a person falls asleep, the metabolic rate of one's body decreases. Thus, initially the fan/cooler needs to be run at full speed. As time passes, one has to get up again and again to adjust the speed of the fan/cooler. We have taken an endeavor to develop a circuit that makes the fan run at full speed for a pre-detemiined time. The speed is decreased to medium after some time, and to slow later on. After a period of about eight hours, the fan /cooler must be switched off.

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Presented By:
Lakshmi Mohan Meera.R
Mibi Ramakrishnan
Guided by Mr.Asni.H Ms.Sumol.N.C

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CONTENTS
Page
1. INTRODUCTION 1
2. BLOCK DIAGRAM 2
3. CIRCUIT DIAGRAM 3-5
4. CIRCUIT DESCRIPTION AND WORKING 6-8
5. PCB FABRICATION 9-14
6. PCB LAYOUT 15
7. COMPONENT LAYOUT 16
8. COST ESTIMATION 17-18
9. CONCLUSION 19
10. REFERENCES 20
11.DATA SHEET
INTRODUCTION
In today's world, one of the most common reason for power shortage is wastage of the same by humans. We often forget to switch off fan /light and other devices after its use. Here, we have taken a small step to solve this problem by designing a simple, low cost, compact circuit that can be used to pre-set the time of work of an electronic device.
We have concentrated mainly on fan/coolers. So speed variation for its working has also been added in the circuit. By using a few additional components, the circuit can be modified into an alarm circuit along with its earlier function. The fact that the device can be turned on/off with torchlight is an added comfort to the user.
BLOCK DIAGRAM
CONTROL CIRCUIT
POWER SUPPLY
LDR
NE555 INPUT SENSOR CIRCUIT D FLIP-FLOP DECISION MAKING CIRCUIT
i
OUTPUT RELAY
CONTROL
CIRCUIT
REGULATORY | CIRCUIT
DECADE COUNTER
r
RELAY CONTROL
r
OSCILLATOR
4 TIMER
OUTPUT FAN
CONTROL
CIRCUIT
POWER SUPPLY
IN4.007
-Df-
LM7S05C
0
0
IN D T
6
ac
+5V
looo/u 25 V -
looop 25 V
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CONTROL CIRCUIT
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SPOT RE LAY
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RE&ULATORY CIRCUIT
CIRCUIT DESCRIPTION AND WORKING
The entire circuit is divided into two parts: control circuit and regulatory circuit. The control circuit is used to turn on/off the device. It provides the supply voltage to the regulatory circuit. The regulatory circuit is used to provide the variation in the speed of fan and to turn it off after the set time.
CONTROL CIRCUIT
This circuit lets you turn on/off a fan by just directing torchlight or other light toward its light dependent resistor. The circuit is powered from a 5v supply
Preset VR1 and a light dependent resistor (LDR) work as the potential divider. Normally, the LDR's resistance is high (20 kilo-ohms) in darkness and low (2 kilo-ohms) in light. This value of high and low resistance varies for other LDR's. Preset VR1 is used for setting the intensity of light, while Preset VR2 is used for setting the output time period of IC1.
When light falls on the LDR, the monostable (IC1) triggers at pin 2, making the output at pin3 from low to high. This low-to -high transition forms a clock for D flip-flop. The D flip-flop is operated in toggle mode by connecting its Q' output to D point. The flip-flop output goes to an inverter (Nl). The inverter output is fed to the relay driver transistor.
When the inverter output is low , diode Dl conducts and the current is diverted into the inverter .Hence the relay does not energize. When the inverter output is high, diode D2 conducts and the current is diverted into the transistor Tl. Hence the relay energizes.When the relay energizes, the regulatory circuit turns on. Otherwise, the fan remains off.
Paste a piece of paper on the face of the LDR so that it doesn't get activated by ambient light. Use a torch to light the LDR.
Initial resetting of monostable and D flip-flop makes the inverter output go high and the regulatory circuit turns on.
When light falls on the LDR, the regulatory circuit goes off. If torchlight is again directed towards the LDR, the fan connected to the output of regulatory circuit turns on. The sequence repeats.
REGULATORY CIRCUIT
The regulatory circuit is powered by the control circuit output.The normally open contact of the control circuit relay is connected to provide supply as shown in circuit diagram.The regulatory circuit makes the fan run at full speed for a pre-determined time. The speed decreases to medium after sometime, and to slow later on. After a period of about eight hours, the fan/cooler is switched off. IC3 (555) is used as an astable multivibrator to generate clock pulse. The pulse is fed to decade divider/counters formed by IC4 and IC5. These ICs act as divide-by-10 and divide-by-9 counters, respectively. The values of capacitor C3 and resistors R5 and R6 are adjusted that the final output of IC5 goes high after about eight hours.
The first two outputs of IC5 (Q0 and Ql) are connected (Ored) via diodes Dl and D2 to the base of transistor T2. Initially output Q0 is high and therefore relay R2 is energized. It remains energized when Ql becomes high. It can be seen that the fan/cooler get the AXC supply directly from the control circuit, and so it shall run at top speed. When output Q2 becomes high and Ql becomes low, relay RL2 is turned 'off and relay RL3 is activated. The fan now runs at low speed.
Throughout the process, pinl 1 of IC is low, so T4 is cut off, thus keeping T5 in saturation and RL4 'on'. At the end of the cycle, when pinl 1 (Q9) becomes high, T4 gets saturated .At the same time Q9 output is fed back as a clock pulse for the D flip-flop. This second clock will make the output of Q of D flip-flop high. Following this, the first relay is released. Thus the supply voltage for the regulatory circuit is disconnected, and the fan/cooler is switched off.
The circuit described above, makes the fan ran at high speed for comparatively lesser time when either Q0 or Ql output is high. At medium speed, it will run for a moderate time period when any of three outputs Q2 through Q4 is high, while at low speed, it will run for a much longer time period when any four outputs Q5 through Q8 is high.
If one wishes, one can run the fan at the three speeds for an equal amount of time by connecting three decimal decoded
outputs of ICS to each of the transistor T2 to T4.0ne can also get more than three speeds by using an additional relay, transistor, and associated components, and connecting one or more outputs of IC5 to it.
In the motor used in certain coolers there are separate windings for separate speeds. Such coolers do not use a rheostat type speed regulator. Usually tapped resistors are used in manually controlled fan-speed regulators. Alternatively, wire-wound resistors of suitable wattage and resistance can be used.
PCB FABRICATION
PCB Artwork (Dip Trace)
Screen printing (Poly blue)
PCB Artwork on tracing sheet
PCB Artwork on Cu plate using paint
Etching (FerricChloride)
Removal of paint from Copper plate by scrubbing
Drying
Drilling (0.9mm Bit) and Cleaning
Printed Circuit Board (PCB) is a piece of art. The performance of an electronic circuit depends on the layout and design of PCB. A PCB mechanically supports and connects components by conductive pathways, etched from copper sheets laminated on to insulated substrate. PCB's are used to route electrical currents and signals through copper tracks which are firmly bonded to an insulating base.
PCB Fabrication involves the following steps:-
1. Drawing the layout of the PCB in a paper. The track layout of
the electronic circuit should be made in such a manner that the paths are in easy routes. It is then transferred to a Mylar sheet. The sheet is then touched with black ink.
2. The solder side of the Mylar sheet is placed on the shiny side of
the five-star sheet and is placed in a frame. Then it is exposed to sunlight with Mylar sheet facing the sunlight.
3. The exposed five-star sheet is put in Hydrogen Peroxide
solution. Then it is put in hot water and shook till unexposed region becomes transparent.
4. This is put in cold water and then the rough side is stuck on to
the silk screen. This is then pressed and dried well.
5. The plastic sheet of the five-star sheet is removed leaving the
pattern on the screen.
6. A Copper clad sheet is cut to the size and cleaned. This is
placed under the screen.
7. Acid resistant ink is spread on the screen so that a pattern of
tracks and a pad is obtained on the Copper clad sheet. It is then dried.
8. The dried sheet is then etched using Feme chloride
solution(32Baume) till all the unwanted copper is etched away. Swish the board to keep the etch fluid moving. Lift up the PCB and check whether all the unwanted copper is removed. Etching is done by immersing the marked Copper clad in Ferric Chloride solution. After that the etched sheet is dried.
9. The unwanted resist ink is removed using Sodium Hydroxide solution. Holes are j:hen drilled.
PCB PARAMETERS
Copper thickness Track width Clearance Pad width Pad height Pad shape Pad hole size On board Hole size Base
PCB quality
-72mil (1mm = 39.37 mils)
- 60mil
- 60mil
- 86mil
- 86mil -Oval
- 25mil
- Through
- 0.9mm (36mil)
- Paper phenolic, hylam -FRC4
SOLDERING
Soldering is the process of joining metals by using lower melting point to weld or alloy with joining surfaces.
SOLDER
Solder is the joining material that melts below 427 degree
connections between components. The popularly used solders are alloys of tin (Sn) and lead (Pb) that melts below the melting point of tin.
Types:
1. Rosin core: - 60/40 Sn/Pb and 63/67 Sn/Pb solders are the most common types used for electronics assembly. These solders are available in various diameters and are most appropriate for small electronics work (0.02"-0.05" dia. is recommended)
2. Lead free: - Lead free solders are used as more environmental
- friendly substitutes for leaded solder, but they are typically not as easy to use mainly because of their higher melting point and poorer wetting properties.
3. Silver: - Silver solders are typically used for low resistance
connections but they have a higher melting point and are more expensive than Sn/Pb solders.
4. Acid-Core: - Acid-core solders should not be used for
electronics. They are intended for plumbing or non-electronics assembly work. The acid-core flux will cause corrosion of circuitry and can damage components.
5. Other special solders:-
¦ Various melting point eutetics: These special solders are
typically used for non-electronics assembly of difficult to construct mechanical items that mist be assembled in a particular sequence.
¦ Paste solders: These solders are used in field applications or
in specialized manufacturing applications.
Flux
In order to make the surface accept the solder readily, the components terminals should be free oxides and other obstructing films. The lead should be cleaned chemically or by abrasion using blades or knives.
Small amount of lead coating can be done on the portion of the leads using soldering iron. This process is called tinning. Zinc chloride or Ammonium chloride separately or in combination is mostly used as fluxes. These are available in petroleum jelly as paste flux.
Flux is a medium used to remove the degree of wetting. The desirable properties of flux are:-
¦ It should provide a liquid cover over the materials and exclude
air gap up to the soldering temperature. c It should dissolve any oxide on the metal surface.
13
¦ It should be easily displaced from the metal by the molten
soldering operation.
¦ Residues should be removable after completing soldering
operation.
The most common flux used in hand soldering of electronic components is rosin, a combination of mild organic acids extracted from pine trees.
Soldering Iron
It is the tool used to melt the solder and apply it at the joint in the circuit. It operates in 230V supply. The iron bit at the tip gets heated while few minutes. The 50W and 25W soldering irons are commonly used for soldering of electronic circuits.
Soldering Steps
1. Make the layout of the components in the circuit. Plug in the
chord of the soldering iron into the mains to get heated.
2. Straighten and clean the components leads using a blade or a
knife. Apply a little flux on the leads. Care must be taken to avoid the components getting heated up.
3. Mount the components on the PCB by bending the leads of the
components. Use nose pliers.
4. Apply flux on the joints and solder the joints. Soldering must be
done in minimum time to avoid diy soldering and heating up of the components.
5. Wash the residue using water and brush.
6. Solder joints should be inspected when completed to determine
if they have been properly made.
> Qualities of a good solder joint:
A) Shiny surface.
B) Good, smooth fillet.
> Qualities of a poor solder joint:
1. Dull or crystallized surfaces: - This is an indicator of a cold solder joint. Cold solder joints result from moving the components after the soldering has been removed but before the solder has hardened. Cold solder joints may work at first but will eventually fail.
2. Air pockets: - Air pockets (voids) result from incomplete wetting of surfaces, allowing air to be in contact with the connecting metals. This will cause oxidation of the joint and eventual failure. Blowholes can occur due to vaporization of the moisture on the surface of the board and exiting through the molten solder. Boards should be clean and dry prior to soldering. Ethanol (100%) can be used as a moisture chaser if boards are wet prior to soldering.
3. Dimples: - Dimples in the surface do not always indicate a serious problem, but they should be avoided since they are precursors to voids.
4. Floaters: - Black spots "floating" in the soldering fillet should be avoided because they indicate contamination and a potential for failure as in the case of voids. These black spots usually result from overheated (burnt) Rosin or other contaminants such as burnt wire insulation. Maintaining a clean tip will help to avoid these problems.
5. Balls: - A solder ball, instead of a fillet can occur if the trace was heated but the lead was not (vice-versa). This prevents proper wetting of both surfaces and results in solder being attached to only one surface (Component or trace).
6. Excess solder: - Excess solder usage can cover up other potential problems and should be avoided. It can also lead to solder bridges. In addition, spherical solder joints can result from the application of too much solder.
PCB LAYOUT
inOAVI !N3NOdlAIO0
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COST ESTIMATION
COMPONENTS QTY RATE COST
LDR 'PVC'(5 MM) 1 4.25 4.25
16 MM (PVC) POT METER (47K) 1 5.00 5.00
VARIABLE RESISTOR 2 4.25 8.50
47 MFD 25 V ELE.CAPACITOR 1 0.40 0.40
NE 555 'ST' 2 2.60 5.20
RESISTOR 10 0.25 25.00
74 HCT 74 1 10.00 10.00
74HCT 04 1 3.65 3.65
1N4007 16 0.35 5.60
BEL 100N (M ) TRANSISTOR 1 4.50 4.50
57DP-06-1C6 RELAY 5 44.00 220.00
CD4017 2 3.85 7.70
BD139 TRANSISTOR 4 6.00 24.00
220 MFD 25V ELE CAPACITOR 1 0.98 0.98
.01 MFD (DISC) CAPACITOR 2 0.12 0.24
PCB 1 1230.00 1230.00
TRANSFORMER 6-0-6 1 58.00 58.00
LM7805 1 8.00 8.00
1000 MFD 25V ELE CAPACITOR 2 4.00 8.00
IC BASE 5 2.00 10.00
MAINS CORD 1 12.00 12.00
TRACK PRINT 1 15.00 15.00
SOLDERING IRON (25W) 1 200.00 200.00
SOLDER & FLUX 1 . 50.00 50.00
BULB(60W) 1 10.00 10.00
TOTAL 1926.02
CONCLUSION
The mini-project has been developed for switching ON/OFF a fan by using torchlight. The speed of the fan can be varied as per our desire by making appropriate changes in circuit design. The fan turns off after a pre-determined time. This circuit with slight modifications can be used as an alarm circuit. Also this is helpful in saving power and bringing comfort.
REFERENCE
1. OP-AMPS and Linear Integrated Circuits by Ramakant A. Gayakwad
2. Digital fundamentals by Floyd & Jain
3. fairchildsemi.com
4. ti.com
5. google.com
PAIRCHILD
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SEMICONDUCTOR'
1N4001 -1N4007
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Features
¦ Low forward voltage drop. ¢ High surge current capability.
General Purpose Rectifiers
©2003 Fairchild Semiconductor Corporation
1N4001-1N40O7, Rev C1
General Purpose Rectifiers
(continued)
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Typical Characteristics
Forward Current Derating Curve
Forward Characteristics
Z
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Non-Repetitive Surge Current
Reverse Characteristics
t 24
P. 1E
1 2 4 6 8 10 20 40 60
NUMBER OF CYCLES AT 60Hz
0 20 40 60 80 100 120 140 RATED PEAK REVERSE VOLTAGE (%)
122003 Fairchild Semiconductor Corporation
1N4001-1N4007. Rev C1
F=/\IRCHIl_D
EM I CONDUCTOR*
March 2008
74LCX74
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Features
¦ 5V tolerant inputs
¦ 2.3V-3.6V Vcc specifications provided
¦ 7.0ns tPD max. (Vcc = 3.3V), 10uA lCc ma*-
¦ Power down high impedance inputs and outputs
¦ ±24mA output drive (Vcc = 3.0V)
¦ Implements patented noise/EMI reduction circuitry
¦ Latch-up performance exceeds JEDEC 78 conditions
¦ ESD performance:
- Human body model > 2000V
- Machine model > 200V
¦ Leadless Pb-Free DQFN package
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
¦ LOW input to SD (Set) sets Q to HIGH level
¦ LOW input to CD (Clear) sets Q to LOW level
¦ Clear and Set are independent of clock
¦ Simultaneous LOW on CD and SD makes both Q and Q HIGH
Ordering Information
Order Number Package Number Package Description
74LCX74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX74BQX<1> MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
74LCX74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering number.
/All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagrams
Pin Assignments for SOIC, SOP, and TSSOP
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12
"CC ^2
CP,
JD1
CP, D,
10
¢i CP2 Q2 Q2
¦CP,
^D2
GND ¦
I”Jc.
CP,
Logic Symbols
^1
T

Q2
CP,
°2
^2
Pad Assignment for DQFN
Truth Table
(Each Half)
(Top View)
Pin Description
Pin Names Description
Di,D2 Data Inputs
CP-,, CP2 Clock Pulse Inputs
CDI. CD2 Direct Clear Inputs
SDL SD2 Direct Set Inputs
Qi,Qi, Q2,Q2 Outputs
Inputs Outputs
SD CD CP D Q Q
L H X X H L
H L X X L H
L L X X H H
H H J- H H L
H H y L L H
H H L X Qo Qo
H = HIGH Voltage Level L = LOW Voltage Level X= Immaterial
j~ = LOW-to-HIGH Clock Transition
Qo(Qo) = Previous Q(Q) before LOW-to-HIGH Transition of Clock
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Rating
Vcc Supply Voltage -0.5V to +7.0V
V, DC Input Voltage -0.5V to +7.0V
v0 DC Output Voltage, Output in HIGH or LOW State(2) -0.5V to Vcc + 0.5V
'IK DC Input Diode Current, V, < GND -50mA
¦OK DC Output Diode Current V0 < GND -50mA
v0>vcc +50mA
lo DC Output Source/Sink Current ±50mA
¢cc . DC Supply Current per Supply Pin ±100mA
!GND DC Ground Current per Ground Pin ± 100mA
TSTG Storage Temperature -65°Cto+150°C
Note:
2. I0 Absolute Maximum Rating must be observed.
Recommended Operating Conditions^
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Min. Max. Units
Vcc Supply Voltage Operating 2.0 3.6 V
Data Retention 1.5 3.6
v. Input Voltage 0 5.5 V
V0 Output Voltage, HIGH or LOW State 0 Vcc V
¦OH/'OL Output Current Vcc = 3.0V-3.6V +24 mA
Vcc = 2.7V-3.0V ±12
Vcc = 2.3V-2.7V ±8
TA Free-Air Operating Temperature ^to 85 °C
At/AV Input Edge Rate, V,N = 0.8V-2.0V, Vcc = 3.0V 0 10 ns/V
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter Vcc (V) Conditions TA = -40°C to +85°C Units



Min. Max.
V|H HIGH Level Input Voltage 2.3-2.7 1.7 V

2.7-3.6
2.0
V,L LOW Level Input Voltage 2.3-2.7 0.7 V

2.7-3.6
0.8.
V0H ' HIGH Level Output Voltage 2.3-3.6 lOH = -100uA VCC-0-2 V

2.3 lOH = -8mA 1.8

2.7 l0H = -12mA 2.2

3.0 'OH =-18mA 2.4


lOH=-24mA 2.2
VOL LOW Level Output Voltage 2.3-3.6 l0L= 100uA 0.2 V

2.3 l0L = 8mA 0.6

2.7 l0L= 12mA 0.4

3.0 l0L= 16mA 0.4


l0L = 24mA 0.55
li Input Leakage Current 2.3-3.6 0 < V, < 5.5V ±5.0 uA
'OFF Power-Off Leakage Current 0 V, orV0 = 5.5V 10 uA
'cc Quiescent Supply Current 2.3-3.6 V,=VCC or GND 10 uA


3.6V <V,< 5.5V ±10
AICC Increase in lcc per Input 2.3-3.6 V|H= Vcc -0.6V 500 MA
AC Electrical Characteristics
Symbol Parameter TA = -40°C to +85°C, RL = 500Q Units

Vcc = 3.3V ± 0.3V, CL = 50pF Vcc = 2-7V, CL = 50pF Vcc = 2.5V ± 0.2V, CL = 30pF

Min. Max. Min. Max. Min. Max.
TMAX Maximum Clock Frequency 150 150 150 MHz
tpHL. lPLH Propagation Delay, CPntoQn orQn 1.5 7.0 1.5 8.0 1.5 8.4 ns
tpHL. {PLH Propagation Delay, CDn or SDn to Qn or Qn 1.5 7.0 1.5 8.0 1.5 8.4 ns
ts Setup Time 2.5 2.5 4.0 ns
tH Hold Time 1.5 1.5 2.0 ns
tw Pulse Width CP 3.3 3.3 4.0 ns
tw Pulse Width and CD, SD 3.3 3.6 4.0 ns
ViEC Recovery Time 2.5 3.0 4.5 ns
lOSHL. 4OSLH Output to Output Skew(4) 1.0 ns
Note:
4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (T-OSHL) or LOW-to-HIGH (t0SLH)-
~4 fa
Dynamic Switching Characteristics
TA = 25°C
Symbol Parameter Vcc (V) Conditions Typical Unit
VOLP Quiet Output Dynamic Peak V0L 3.3 CL = 50pF, V|H = 3.3V, V,L = OV 0.8 V
2.5 CL = 30pF, V|H = 2.5V, V,L = OV 0.6
VOLV Quiet Output Dynamic Valley V0L 3.3 CL = 50pF, V|H = 3.3V, V|L = OV -0.8 V
2.5 CL = 30pF, V,H = 2.5V, V,L = OV -0.6
Capacitance
Symbol Parameter Conditions Typical Units
CIN Input Capacitance VCc = Open, V, = OV or Vcc 7 PF
CoUT Output Capacitance Vcc = 3.3V, V, = OV orVcc 8 PF
CPD Power Dissipation Capacitance Vcc = 3.3V, V, = OV or Vcc, f = 10MHz 25 PF
AG Loading and Waveforms (Generic for lcx Family)
O
X
VLH-VHI
Test Switch
VZH-'PH; tpLH. tpHL Open
WL. 'PLZ 6V at Vcc = 3.3 ± 0.3V
Vcc x 2 at Vcc = 2.5 ± 0.2V
tpZH. tpHZ GND
Figure 1. AC Test Circuit (CL includes probe and jig capacitance)
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01 (Q CO
D C
"cc GND
^CONTROL IN
CLOCK
OUTPUT
Waveform for inverting and Non-Inverting Functions
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VHL.
\Vmo

5y OUTPUT ^CONTROL
~”y iS””y*
VzL ”H *PLZ -
-5J-
3-STATE Output Low Enable and Disable Times for Logic
DATA IN .
.^CONTROL I INPUT
CLEAR w-ij”
GND
»< T3 (D
13
O W
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m a ca
CO
3-STATE Output High Enable and Disable Times for Logic
ANY OUTPUT
90% 9 0%
trise and t,a,|
3
en <
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CD 3
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BD135; BD137; BD139
NPN power transistors
Product specification 1999 Apr 12
Supersedes data of 1997 Mar 04
SEMICONDUCTORS
NPN power transistors
BD135; BD137; BD139
FEATURES
¢ High current (max. 1.5 A)
¢ Low voltage (max. 80 V).
APPLICATIONS
» Driver stages in hi-fi amplifiers and television circuits. DESCRIPTION
NPN power transistor in a TO-126; SOT32 plastic package. PNP complements: BD136, BD138 and BD140.
PINNING
PIN DESCRIPTION
1 emitter
2 collector, connected to metal part of mounting surface
3 base
3 Top view
'-1
Fig.1 Simplified outline (TO-126; SOT32) and symbol.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCBO collector-base voltage open emitter
BD135 - 45 V
BD137 - 60 V
BD139 - 100 V
VCEO collector-emitter voltage open base
BD135 45 V
BD137 - 60 V
BD139 - 80 V
VEBO emitter-base voltage open collector - 5 V
lc collector current (DC) - 1.5 A
¢CM peak collector current - 2 A
IBM peak base current - 1 A
Plot total power dissipation Tmb ^ 70 °C - 8 w
Tstg storage temperature -65 +150 °C
Tj junction temperature - 150 °C
Tamb operating ambient temperature -65 +150 °C
NPN power transistors BD135; BD137; BD139
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 100 K/W
Rth j-mb thermal resistance from junction to mounting base 10 KA/V
Note
1. Refer to TO-126; SOT32 standard mounting conditions.
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
'CBO collector cut-off current lE = 0; VCB = 30 V - - 100 nA
lE = 0;VCB = 30 V;Tj= 125 °C - - 10 uA
'EBO emitter cut-off current lc = 0; VEB = 5 V 1 - 100 nA
hFE DC current gain VCE = 2 V; (see Fig.2) lc = 5 mA lc = 150 mA lc = 500 mA 40
63 25 - 250
DC current gain lc = 150 mA; VCE = 2V;
BD135-10; BD137-10; BD139-10 (see Fig.2) 63 - 160
BD135-16; BD137-16; BD139-16 100 - 250
VcEsat collector-emitter saturation voltage lc = 500 mA; lB = 50 mA - - 0.5 V
VBE base-emitter voltage lc = 500 mA; VCE = 2 V - - 1 V
fT transition frequency lc = 50 mA; VCE = 5 V; f = 100 MHz - 190 - MHz
hFE1 hFE2 DC current gain ratio of the complementary pairs |lcl = 150 mA; |VCEI =2 V 1.3 1.6
160 NFE 120
80
40
NPN power transistors BD135; BD137; BD139
MBHT29
VCE = 2 V




\
\ \

I
10"1 1 10 102 ,C(MA) 103
Fig.2 DC current gain; typical values.
SILICON TRANSISTORS
SEMICONDUCTORS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS AT TJ»25*C
TYPE NPN [PNP Po PD TI-28«C Tc-25'C
W W Vcao
V VCEO V VEBO V Ic ' mA hfE © Vct/lc mirt'max V/mA VCE(UI) @ Ic/ta
max
V mA/mA <T
(WP) MHz IctO <!H>)
nA Col, dye) PF Cast
^/2N3701 0.5 1.8 140 80 7 1000 40/120 10/150 0.2 150/15 80 10 12 TO-18
./2N4030 0.8 4 60 60 5 1000 40/120 5/100 0.5 500/50 100 60 20 TO-39
7y/2N4031 0.8 4 80 80 S 1000 40/120 6/100 0.5 600/50 100 60 20 ¦ TO-39
/V*2N4032 0.8 4 60 60 £ 1000 100/300 5/100 0.5 500/50 150 50 20 TO-39
/" X2N4033 0.8 4 80 60 5 1000 100/300 5/100 0.5 600/50 160 60 20 TO-39
I J3CY11S 0.6 3 60 60 9 250 12/- 2/30 - - 100 100 - TO-39
' ^KlOO 0.8 4 60 SO 6 500 40/300 6/160 - - 100 1000 20 TO-39
1 IfStaOOA 0.8 4 60 50 6 500 40/120 6/150 - - 100 1000 20 TO-39
\. L'SKLOOB 0.8 4 60 60 6 500 100/300 6/150 - - 100 1000 20 TO-39
Jv^'-JiSK100H 0.8 4 80 60 6 1000 100/300 5/150 0.3 150/15 150 1000 20 TO-39
\j^KlOl - 0.8 4 40 ' 30 6 500 40/300 5/150 - 100 1000 20 TO-39
y.SK102 0.8 4__ 30 ¦ 30 3.5 1000 40/300 5/600 - - - 100 1000 20 TO-39
BLIOO 0.8 4 60 50 6 EOO 40/300 5/150 - - 100 1000 20 TO-39
C SL1O0A 0.8 4 60 50 6 600 40/120 6/150 - - 100 1000 20 TO-39
\}i EL1008 0.8 4 60 50 6 500 100/300 6/150 - - 100 1000 20 TO-39
* SL100H 0.8 5 80 60 7 1000 100/300 5/150 0.3 150/15 100 1000 15 TO-39
¢SL101 0.8 4 40 30 6 500 40/300 5/150 - - 100 1000 20 TO-39
SL102 0.8 4 30 30 3.5 1000 40/300 5/500 - 100 1000 20 TO-39
./VSF103 0.4 1.8 30 24 5 250 40/300 6/150 - - 250 1000 8 TO-18
'"£,60103 0.4 1.8 30 24 5 250 40/300 5/150 - - 250 1000 8 TO-18
' /-BFX 84 0.8 - 100 60 5 1000 30/- 10/150 0.35 150/15 50 500 - TO-39
. / BFX 85 0.8 - 100 60 5 1000 70/- 10/150 0.35 150/15 50 500 - TO-39
> \ BFX 86 0.8 - 40 35 5 1000 70/- 10/150 0.35 150/15 50 500 - TO-39
© Audio output matched pairs
[
TYPE NPN PNP '
C 369
R/SY/C I88B
BC 368
mA
PD mw
800
800
800
800
VCBO V
25
25
25
25
VCEO V
20
20
20
20
VEBO V
5.0
5.0
5.0
5.0
IC A
1.5
1.5
1.0
1.0
riFE © VCE/ IC min^max V/mA
* 30-375 IV/500
* 80-375 IV/500
85-375 IV/500
85-375 IV/500
0.5
VCE (sal) <s> Ic/IB V A/mA
0.5
10
1/500 10
0.5
10
10
0.5
1/500
1/500
1/500
fT
(TYPL
MHz
60
60
65
65
TO-92+ TO-92+
TO-92+ TO-92+
HFEI/HFE2 DC CURRENT GAIN RATIO OF MATCHED PAIR 187/188
1.4 6 IC=500 MA/VcE^V
(d) Medium speed switches
CASE OUTLINES
. DO-7 DO-35 SOT-25
TO-18 TO-39 TO-66
Note : Dimensions in nun unless otherwise specified
TO-96 TO-99 TO-105 TO-106
Note : Dimensions in mm unless otherwise specified
F=AIRCHILD
SEMICONDUCTOR8
fairchildsemi.com
LM555/NE555/SA555
Single Timer
Features
¢ HIGH CURRENT DRIVE CAPABILITY (200MA)
¢ ADJUSTABLE DUTY CYCLE
' TEMPERATURE STABILITY OF 0.005%/°C 3 TIMING FROM |ISEC TO HOURS
¢ TURN OFF TIME LESS THAN 2U,SEC
Applications
" PRECISION TIMING
¢ PULSE GENERATION
¢ TIME DELAY GENERATION
¢ SEQUENTIAL TIMING
Description
THE LM555/NE555/SA555 IS A HIGHLY STABLE CONTROLLER CAPABLE OF PRODUCING ACCURATE TIMING PULSES. WITH MONOSTABLE OPERATION, THE TIME DELAY IS CONTROLLED BY ONE EXTERNAL RESISTOR AND ONE CAPACITOR. WITH ASTABLE OPERATION, THE FREQUENCY AND DUTY CYCLE ARE ACCURATELY CONTROLLED WITH TWO EXTERNAL RESISTORS AND ONE CAPACITOR.
Internal Block Diagram
GND 0” ww-
-VWV-
-A/vVv”(8)VcC
DISCHARGING TR.
©Discharge
OutputQ}”
OUTPUT
STAGE
F/F
Reset
RNI VREF
1 O
Control VOLTAGE
©2002 Fairchild Semiconductor Corporation
Rev. 1.0.2
Absolute Maximum Ratings (Ta = 25°C)
Parameter Symbol Value Unit
Supply Voltage Vcc 16 V
Lead Temperature (Soldering 10sec) TLEAD 300 °C
Power Dissipation PD 600 mW
Operating Temperature Range
LM555/NE555
SA555 TOPR 0-+70 -40 ~ +85 °C
Storage Temperature Range TSTG -65-+150 °C
Electrical Characteristics
(TA = 25°C, Vcc = 5 ~ 15V, unless otherwise specified)
Parameter Symbol Conditions Min. Typ. Max. Unit
Supply Voltage VCC - 4.5 - 16 V
Supply Current *1(Low Stable) ice VCC = 5V, RL = ~ - 3 6 mA

VCC = 15V, RL = °° - 7.5 15 mA
Timing Error*2 (Monostable) Initial Accuracy Drift with Temperature Drift with Supply Voltage ACCUR
At/AT At/AVcC RA= ikntoiookn
C = 0.1uF - 1.0 .
50
0.1 3.0 0.5 %
ppm/°C %A/
Timing Error *2(Astable) Intial Accuracy Drift with Temperature Drift with Supply Voltage ACCUR
At/AT At/AVcC RA = 1knto 100kQ C = 0.1uF - 2.25 150 0.3 - %
ppm/°C %/V
Control Voltage VC Vcc=15V 9.0 10.0 11.0 V

VCC = 5V 2.6 3.33 4.0 V
Threshold Voltage VTH VCC=15V - 10.0 - V

Vcc = 5V - 3.33 - V
Threshold Current *3 ITH - - 0.1 0.25 uA
Trigger Voltage VTR VCC = 5V 1.1 1.67 2.2 V

Vcc=15V 4.5 5 5.6 V
Trigger Current ITR VTR = OV 0.01 2.0 uA
Reset Voltage VRST - 0.4 0.7 1.0 V
Reset Current IRST - 0.1 0.4 mA
Low Output Voltage VOL Vcc=15V ISINK= 10mA ISINK = 50mA - 0.06 0.3 0.25 0.75 V V

VCC = 5V ISINK = 5mA - 0.05 0.35 V
High Output Voltage VOH Vcc = 15V ISOURCE = 200mA ISOURCE = 100mA 12.75 12.5 13.3 - V ¦ V

VCC = 5V ISOURCE = 100mA 2.75 3.3 - V
Rise Time of Output tR - - 100 - ns
Fall Time of Output tF - - 100 - ns
Discharge Leakage Current ILKG . - - 20 100 nA
Notes:
1. Supply current when output is high is typically 1mA less at Vcc = 5V
2. Tested at Vcc = 5.0V and Vcc = 15V
3. This will determine maximum value of RA + RB for 15V operation, the max. total R = 20MC1, and for 5V operation the max. total R = 6.7Ma
Application Information
Table 1 below is the basic operating table of 555 timer:
Table 1. Basic Operating Table
Threshold Voltage (Vth)(PIN 6) Trigger Voltage (Vtr)(PIN 2) Reset(PIN 4) Output(PIN 3) Discharging Tr. (PIN 7)
Don't care Don't care Low Low ON
Vth > 2Vcc / 3 Vth > 2Vcc / 3 High Low ON
Vcc / 3 < Vth < 2 Vcc / 3 Vcc/3<Vth<2Vcc/3 High - -
Vth < Vcc / 3 Vth < Vcc/3 High High OFF
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, timer's output changes according to threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
1. Monostable Operation
Time Delay(s)
Figure 1. Monoatable Circuit Figure 2. Resistance and Capacitance vs.
Time delay(td)
+Vcc
Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time.
The voltage across the external capacitor CI, Vci increases exponentially with the time constant i=RA*C and reaches 2Vcc/3
at td=l. 1RA*C Hence, capacitor CI is charged through resistor RA. The greater the time constant RAC, the longer it takes
for the Vci to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width.
When the applied voltage to the capacitor CI reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,
turning the discharging Tr. on. At this time, CI begins to discharge and the timer output converts to low.
In this way, the timer operating in monostable repeats the above process. Figure 2 shows the time constant relationship based
on RA and C Figure 3 shows the general waveforms during monostable operation.
It must be noted that, for normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform not operate properly if the trigger pulse voltage at the end of the output pulse remains at below Vcc/3. Figure 4 shows such timer output abnormality.
i ”1

| Tri >ger
1
Output nil ¦ +- 1 J
u L
Thrc> hold r
/ 1/ /
RA=».lkO, RL=1ktJ, Cl=0.01uF, Vcc=5V
Figure 5. Astable Circuit
Figure 4. Waveforms of Monostable Operation (abnormal) 2. Astable Operation
Figure 7. Waveforms of Astable Operation
An astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi vibrator. When the timer output is high, its internal discharging Tr. turns off and the Vci increases by exponential function with the time constant (RA+RB)*C.
When the Vci, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high, resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the CI discharges through the discharging channel formed by RB and the discharging Tr. When the Vci falls below Vcc/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the Vci rises again.
In the above process, the section where the timer output is high is the time it takes for the Vci to rise from Vcc/3 to 2Vcc/3, and the section where the timer output is low is the time it takes for the Vc 1 to drop from 2Vcc/3 to Vcc/3. When timer output is high, the equivalent circuit for charging capacitor CI is as follows:
Vc 1(0-)=Vcc/3
, dv^ Vcc-V(0-)
'1 D< RA + RB
(1)
VC1(0+> = VCC/3 (2)
1 2
1~3e
f (RA + Re)Cl)L
vC1<l> = VCC
(3)
Since the duration of the timer output high state(tH) is the amount of time it takes for the Vci(t) to reach 2Vcc/3,
A3
vci«) = !vcc-vcc
1ie
(RA+RB)C1
(4)
tH = C1(RA + RB)ln2 = 0.693(RA+RB)C1 (5)
The equivalent circuit for discharging capacitor CI when timer output is low as follows:
DVC1 ' 1
Ci^+R^vcr° (6)
t
2 (R,+RD)C1
VClW = 3Vcce <7>
Since the duration of the timer output low state(tL) is the amount of time it takes for the Vci(t) to reach Vcc/3,
hrn = 2-y <Ra+Rd)C1
3VCC 3Vcce
(8)
tL = C1(RB + RD)ln2 = 0.693(RB + RD)C1 (9)
Since RD is normally RB»RD although related to the size of discharging Tr.,
tL=0.693RBCl (10)
Consequently, if the timer operates in astable, the period is the same with
T=tH+tL=0.693(RA+RB)Ci+0.693RBCl=0.693(RA+2RB)Cf because the period is the sum of the charge time and discharge time. And since frequency is the reciprocal of the period, the following applies.
frequency, f =
1.44
T (RA + 2RB)C1
(11)
3. Frequency divider
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.
Texas Instruments
Data sheet acquired from Hams Semiconductor
SCHS027C - Revised February 20f^
CMOS Counter/Dividers
High Voltage Types (20-Volt Rating) CD4017B-Decade Counter with
10 Decoded Outputs CD4022B-Octal Counter with
8 Decoded Outputs
¦ CD4017B and CD4022B are 5-stage and 4-stage Johnson counters having 10 and 8 decoded outputs, respectively Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT signal. Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times.
These counters are advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. A high RESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high-speed operation. 2-input decode-gating and spike-free de¬coded outputs. Ami lock gating is provided, thus assuring proper counting sequence. The decoded outputs are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 clock input cycles in the CD4017B or every 8 clock input cycles in the CO4022B and is used to ripple-clock the succeeding device in a multi-device counting chain.
RECOMMENDED OPERATING CONDITIONS

-I_-L-
_I_"T-


”¢Â»-

_I_-7-
-I-V
(6 "
6
CUNT
OUR
CD4017B, CD4022B Types
CVOCK-
Features:
¦ Fully static operation
¦ Medium-speed operation . . . 10 MHz (typ.)at VOD- 10 V
¦ Standardized, symmetrical output characteristics
¦ 100% tested for quiescent current at 20 V
¦ 5-V, 10-V, and 15-V parametric ratings
¦ Meets all requirements of JEDEC Tentative Standard No, 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"
CO4017B Functional Diagram
Applications:

14 JL--0-]
CLOCK 'S
IIWIHT mil ” J
OUT.
!”¢>¢ o
n -4- o
u
2 "3* a
1”¦¦*¢
¢DO' *
¢55 : « i|
CARRY
OUT

WCS-J5
CD4022B
Functional Daflrton

* - "oe
o t 14 ” ncscT
” OOOt
2 ” 1} ” CLOCK IMNWT
i - 12 ” c&rmr our
J ”H to ” 4
V« ” ¢ ” ft
* Decade counter/decimal decode display (CD4017B)
¦ Binary counter/decoder " Frequency division
¦ Counter control/timers
¢ Divide-by-N counting
¦ For further application information, see ICAN-6166 "COS/MOS MSI Counter and Register Design and Applications"
TOP VIEW CO4017B TERMINAL DIAGRAM
"OO
I” RESET . CLOCK
HOCK MMNUR
I CKK-KY 007
»CI-«444ft<
NC
top view
NO CONNECTION
CO4022B
TERMINAL DIAGHAM
The CD4017B and CD4022B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PWand PWR suffixes). The CD4017B types also are supplied in 16-lead small-outline packages (M and M96 suffixes).
|o a
O -J OC O fuj »
isi
Copyright 53 2004, Texas Instruments Incorporated
MAXIMUM RATINGS, Absolute-Maximum Values: DC SUPPLY-VOLTAGE RANGE. (VDD)
Voltages referenced to Vgs Terminal) -0.5V to + 20V
INPUT VOLTAGE RANGE, ALL INPUTS -OSVto VDD +°-5v
DC INPUT CURRENT. ANY ONE INPUT ±10mA
POWER DISSIPATION PER PACKAGE (PD>:
For TA - -5S°C to +100°C 500mW
For TA-+10O°C to +12500 Derate Linearity at 1 2mW/°C to 200mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA - FULL PACKAGE-TEMPERATURE RANGE (Alt Package Types) 10OmW
OPERATING-TEMPERATURE RANGE (TA) .... -55°C to +125°C
STORAGE TEMPERATURE RANGE (T8(g) -65°C to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79mm) from casefor 10s max +285°C
i:iiftff|:fi
'Miln^ililti!t»;i;t»!',i|:i'»"'!»l»»w
STATIC ELECTRICAL CHARACTERISTICS
CHARAC¬TERISTIC CONDITIONS LIMITS AT INDICATED TEMPERATURES (°C) U N
1
T S
(VI V|N
(V) VDD
(V) -55 -40 +85 +125 +26







Min. Typ. Max.
Quiescent Device Current,
'DD MAX - 0.5 5 5 5 150 150 - 0,04 5 MA
- 0,10 10 10 10 300 300 - 004 10
- 0,15 15 20 20 600 600 - 0.04 20
0.20 20 100 100 3000 3000 - 0.08 100
Output Low (Sink) Current 'OL 04 0,5 5 0.64 0.61 0.42 0.36 0.51 1 - mA
0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 2.6 -
1.5 0,15 15 4.2 4 28 24 3.4 6.8 -
Output High (Source) Current,
¢OH MIN 4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 -
2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -32 -
9 5 0.10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 -
13 5 0,15 15 -4.2 -4 -28 -2.4 -3.4 -68 -
Output Voltage: Low-Level, VQJ_ Max 0,5 5 005 - 0 0.05 V
0,10 10 0.05 - 0 005
0.15 15 0 05 - 0 0.05
Output Voltage H«gh Level, V0H Mm - 0,5 5 4.95 4 95 5 -
0,10 10 9.95 995 10 -
- 0.15 15 14.95 14,95 15
Input Low Voltdge V(L Max 0.5.4.5 - 5 1.5 - 1.5 V
1,9 - 10 3 - - 3
1.5.13.5 15 4 - - 4
Input High Voltage, V||^ Min 0.5.4.5 - 5 3.5 3.5 - -
1.9 - 10 7 7 -
1.5.13.5 15 11 11 - -
Input Current tjfg Max. - 0,18 18 ±0.1 ±0 1 ±1 ±1 - ±10-5 ±0.1 *iA
-J 2
tr O
2
4-6
ay^ IW»OTS
vss
NOTt
X'M Will KamTiu.i.r. TOWTtl vaowpvu.
COMWCF OIL
»WI tc c it HCH
MCI 1*4*1 jOvfyts
4 »OTl
COMMMTMM
or wvn
wci iwtm ^'«. '4-0>«t«CMt-dMe»-Current tmt circuit.
Fig. t8 - Divide br Ncounter IN < 10) with N decoded outputs.
fif.lt- fnputWf ft circuit.
When the Nth decoded output it retched <Nth dock puis*) the S fi flip flop (con hi ucted from two NOR gain of the CD400IB1 generates a reset puis* which clear, the C04017B or CD4022B to it] ttro count. At th.ii time, ii 'he N* decocted out¬put if greater than or aqutl to 8 In the CO 40) 7B or 5 in the C04022B, the CQUT LIN« goes high to clock the next CO4017B or C0-4022B counter lection. The "0" decoded output also goes high at this time. Coinci¬dence of the clock low and decoded "0" output low resets the S-R (lip (lop to enable the CD4017B cr CO40223. If th> '4'h de¬coded output is lesc than 6 (C()4(1'/BI rir 5 (CD4022B), the CQOT line will not go high and. therefore, cannot be used, in this case "0" decoded output may be used to perform the clocking function for the next counter.
<_> Hi
" 2
kg IS I
CD4017B CE
QO 01 08 OS
HE
CO4017B
QO Ol Q8 09
CO4017B
QO 01 Q8 08
S DECODED OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGE
LAST STAGE
Fig. 19 - Cascading the CD4017B.
~\ , -
4"
V m

r" m
f/ff. 4 - Timing diagram for CD4022B.
'CLOCK
-OH>
®-
@-
CLOCK INHIBIT
«CL-OT4»P,»
CHIP DIMENSIONS AND PAD LAYOUTS
CD4017BH
CD4022BH
Dime/wons m parentheses are m millimeters and jre derived from the basic inch dimensions as in rf't\§tfd Grid graduations are m mils (1Q~3 inch).
Data pack F
Issued March 1997 232-3816
Data Sheet
Light dependent resistors
NORP12 RS stock number 651-507 NSL19-M51 RS stock number 596-141
Two cadmium sulphide (cdS) photoconductive cells with spectral responses similar to that of the human eye. The cell resistance falls with increasing light inten¬sity. Applications include smoke detection, automatic lighting control, batch counting and burglar alarm sys¬tems.
Illumination (Lux)
0.1
50
100
500
30,000
Guide to source illuminations
Light source
Moonlight
60Wbulbat lm
1WMES bulb at 0.1m
Fluorescent lighting
¦Bright sunlight
Circuit symbol

Electrical characteristics
TA = 25°C. 2854°K tungsten light source
Parameter Conditions Min. Typ- Max. Units
Cell resistance 1000 lux 10 lux 400 9 - Q kli
Dark resistance - 1.0 - - Mfi
Dark capacitance - - 3.5 - pF
Rise time 1 1000 lux 10 lux - 2.8 18 ms ms
Fall time 2 1000 lux 10 lux - 48 120 ms ms
1. Dark to 110%RL
2. To 10 x RL
RL = photocell resistance under given illumination. Features
¢ Wide spectral response
¢ Low cost
¢ Wide ambient temperature range.
Dimensions
Light memory characteristics
Light dependent resistors have a particular property in that they remember the lighting conditions in which they have been stored. This memory effect can be minimised by storing the LDRs in light prior to use. Light storage reduces eguihbrium time to reach steady resistance values.
.512 497
13 00' 12 62,
NORP12 (RS stock no. 651-507)
Absolute maximum ratings
Voltage, ac or dc peak
Current
Power dissipation at 30°C
Operating temperature range,
_320V 75mA
250mW
-60°Cto+75°C
.175 liAi .155 3.94
250±010 /6.601 6 10
I
/ 69 \ 58)
i i
- 375±010
Units in inches (millimetres)
Absolute maximum ratings
Voltage, ac or dc peak
Current
Power dissipation at 25°C
Operating temperature range.
Derate linearly from 50mW at 25°C to OW at 75°C. Electrical characteristics
Dimensions
0.140±0.010 (Ml' 3.30
Parameter Conditions Min. Typ. Max. Units
Cell resistance 10 lux 100 lux 20 5 100 m
Dark resistance 10 lux after
10 sec 20 _ Mil
Spectral response - - 550 - urn
Rise time lOftc - 45 - ms
Fall time lOftc - 55 ms
0.165±0.010 1 3.94
1
0015
0.055± 0.010 (IZI)
”, M.14'
1.5
(38.1) NOM
0.020+0.002 0_59 * 0.46 '
0.100±0.0O5 12.41 '
Figure 5 Spectral response
100% 90% 80% 70%
<D V)
c
8- 60%
i 50% n
40% 30% 20% 10% 0%
Typical application circuits Figure 6 SENSITIVE LIGHT OPERATED RELAY
Relay energised when light level increases above the level set by VR
Typical value Rl = lOOkil
R2 = 200kQ preset to give two overlapping ranges. (Calibration should be made against an accurate meter.)
As Figure 6 relay energised when light level drops below the level set by VR,
(Relay energised when light exceeds preset level.) Incorporates a balancing bndge and op-amp. R, and NORP12 may be interchanged for the reverse function.
Adjust turn-on point with VR]
The information provided in RS technical literature is believed to be accurate and reliable; however, RS Components assumes no responsibility for inaccuracies or omissions, or for the use of this information, and all use of such information shall be entirely at the user's own risk.
No responsibility is assumed by RS Components for any infringements of patents or other rights of third parties which may result from its use Specifications shown in RS Components technical literature are subject to change without notice.
RS Components, PO Box 99, Corby, Northants, NN17 9RS Telephone: 01536 201234
Q An Hectrocomponents Company © RS Components 1997
SCLS078B - DECEMBER 1982 - REVISED MAY 1997
Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
description
These devices contain six independent inverters. They perform the Boolean function Y = A in positive logic.
The SN54HC04 is characterized for operation over the full military temperature range of -55°C to 125 C. The SN74HC04 is characterized for operation from -40°C to 85°C.
SN54HC04 ... J OR W PACKAGE SN74HC04 .. . D, DB, N, OR PW PACKAGE (TOP VIEW)
SN54HC04 . .. FK PACKAGE (TOP VIEW)
> < U c, <
t- Z > to
t”ri”li”it”ii”i
3 2 1 20 19
18[ 6Y
17[ NC
16[ 5A
1S[ NC
14 [ 5Y
9 10 11 12 13
nnr~ir~in
logic symbolt
> o o > <
Ci 2 Z **¦ O
NC - No internal connection
1A 2A 3A 4A 5A 6A
11
13
4
L ¢
s S
10
12
1Y 2Y 3Y 4Y 5Y 6Y
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages.
logic diagram (positive logic)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of ail parameters.
Copyrights: 1997,-TexayrnstroivicnU Incuipuialetr-
SCLS078B - DECEMBER 1982 - REVISED MAY 1997
absolute maximum ratings over operating free-air temperature ranget
Supply voltage range, Vqq -0.5 V to 7 V
Input clamp current, l|K (V| < 0 or V| > VCC) (see Note 1) ±20 mA
Output clamp current, I0K (VO < 0 or V0 > VCC) (see Note 1) ±20 mA
Continuous output current, \q (VQ = 0 to V^Q) ±25 mA
Continuous current through VQQ or GND ±50 mA
Package thermal impedance, GJA (see Note 2): D package 127°C/W
DB package 158°C/W
N package 78°C/W
PW package 170"C/W
Storage temperature range, T^g -65°C to 150'C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.
recommended operating conditions
SN54HC04 SN74HC04 UNIT
MIN NOM MAX MIN NOM MAX
Vcc Supply voltage 2 5 6 2 5 6 V
V|H High-level input voltage VCC = 2V 1.5 1.5 V
Vcc = 4.5 V 3.15 3.15
Vcc = 8V 4.2 4.2
V|L Low-level input voltage Vcc = 2V 0 0.5 0 0.5 V
Vcc = 4.5 V 0 1.35 0 1.35
vcc = sv 0 1.8 0 1.8
V| Input voltage o vcc 0 Vcc V
Vo Output voltage 0 Vcc 0 Vcc V
tf Input transition (rise and fall) time VCC = 2V 0 1000 0 1000 ns
Vcc = 4 5V 0 500 0 500
V(X = 6V 0 400 0 400
T/\ Operating free-air temperature -55 125 -40 85 °C
SCLS078B - DECEMBER 1982 - REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS vcc TA«25=C SN54HC04 SN74HC04 UNIT


MIN TYP MAX MIN MAX MIN MAX
2 V 1.9 1.998 1.9 1.9
l0H = "20 uA 4.5 V 4.4 4.499 4.4 4.4
V0H V| = V|HorV|L 6V 5.9 5.999 5.9 5.9 V
'OH = -* "»* 4.5 V 3.98 4.3 3.7 3.84
'OH = -5 2 mA 6 V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
lOL = 20uA 4.5 V 0.001 0.1 0.1 0.1
VOL V| = V|H or V|L 6 V 0.001 0.1 0.1 0.1 V
IQL = 4 mA ¦ 4.5 V 0.17 0.26 0.4 0.33
IQL = 5 2 mA 6 V 0.15 0.26 0.4 0.33
it vl = VCC<>rO 6 V ±0.1 ±100 ±1000 ±1000 nA
ice V| = VQC «" o. io = o 6 V 2 40 20 uA
C| 2 V to 6 V 3 10 10 10 PF
switching characteristics over recommended operating free-air temperature range, C|_ = (unless otherwise noted) (see Figure 1) = 50 pF
PARAMETER FROM TO VCC TA»25 C SN54HC04 SN74HC04 UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
2 V 45 95 145 120
lpd A Y 4.5 V 9 19 29 24 ns
6 V 8 15 25 20
2 V 38 75 110 95
tt Y 4.5 V 8 15 22 19 ns
6 V 6 13 19 16
operating characteristics, = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpfj Power dissipation capacitance per inverter No load 20 PF
SCLS078B - DECEMBER 1982 - REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
Input 30% 1
Test Point
: CL = 50pF (see Note A)
¢0%
LOAD CIRCUIT
,er VCC
] \ IftV Q V
Input -f
In-Phase Output
Out-of-Phase Output
^1
vcc
U-
M>HL
00%
90%
50%
0 V V0H
VOL
”¢I i*”v i ”*i K”tf
IVs »HH-”VOL
”#1 ft” M |4”tr
VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. C\_ includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR s 1 MHz, Zo = 50 a, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tp|_H and tpHL are the same as tprj.
Figure 1. Load Circuit and Voltage Waveforms

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