[attachment=2572]

AUTOMATIC BUS STATION ANNOUNCEMENT SYSTEM
ANTENNA
Message section
3. WORKING EXPLANATION
The above fig shows the complete circuit diagram of automatic bus station announcement system. It consists of a transmitter, receiver (main circuit) and a message section.
Transmitter:
The transmitter circuit transmits the code of each bus from the bus. To generate the code and the address we use an encoder IC HT12E. The encoder has an 8 bit address and 4 bit data lines. Through these bits we can select any code for a bus. The address is used to separate each corporation from one another. To avoid any missing of a bus, the transmitter will activated in a pulsating form. That is the transmitter is in on for some instant and off for next instant. To achieve this we use an astable multivibrator wired around IC 555. The time period is selected as Ton= 2sec and Toff=lsec. The out put of the multivibrator is given to the Enable pin of encoder. During the Toff period, the encoder will be activated, and the address and the code are encoded to a pulse stream and given to the input of ASK transmitter module.
The ASK (amplitude shift keying) module operate at 433MHz range. For logic 1 the carrier will be maximum in amplitude and for 0, the carrier will be minimum to reduce the power consumption. For each bus, a different code is selected through the data line and for each corporation, differrent addres is selected through the address line.
Message section:
0.1 MF
To play back a prerecorded message, we use voice chip APR600. The APR 9600 offers true single chip voiced recording, non-volatile storrasge, and playback capability for 60 seconds. The device supports single and multiple message handling. Here, we use the chip to record 4 different messages.
To record a message put the REC pin to ground through a switch and select the address by pins 1 tO 8. Then speak through the mic. After the recording completed release the REC pin. To playback a message, simply ground the corresponding pin (1 to 8).
The microcontroller selects the address through PORTD and the voice signal will be available at the output. The signal is amplified using an amplifier LM386 and given to the speaker. When the chip is in engaged, microcontroller detects it through the strobe pin and waits for some while.
Receiver:
The transmitted code is received by an ASK receiver at the station and given to the decoder IC HT12D. The decoder has an 8-bit address line and we have to set the address to match the transmitter address. The decoder decodes the received signal and compares the address. If the address is same, the data will be available at the outputs with a strobe signal.
ANTENNA
Microcontroller:
We use PIC16F877A as the controller. It is an 8 bit processor
with 33 input output ports. The main features of the microcontroller are:
¢ High-performance RISC CPU
¢ Only 35 single word instructions to learn
¢ All single cycle instructions except for program branches which are two cycle
¢ Operating speed: DC - 20 MHz clock input
¢ Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM data memory
¢ Pinout compatible to the PIC16C73B/74B/76/77
¢ Interrupt capability (up to 14 sources)
¢ Eight level deep hardware stack
¢ Direct, indirect and relative addressing modes
The microcontroller examines the strobe signal at E0. When a bus entered the station, the receiver receives the code from the bus and gives a strobe to PIC. Then the microcontroller compares the code and identifies the bus and gives the signal to select the message from the voice chip. Also the LCD will be displayed with the details of the bus
5. PROGRAM
list p=16f877 #include pl6f877.inc
CBLOCK 0X20
TEMP
CNT_3ms
cntlms
cnt500us
CNT_2s
CNT_100ms
CNT_500ms
EN DC
ORG 00 GOTO START
TABLE ADDWF PCL,F
RETLW H'30'
RETLW H'31'
RETLW H'32'
RETLW H'33'
RETLW H'34'
RETLW H'35'
RETLW H'36'
RETLW H'37'
RETLW H'38'
RETLW H'39'
5
START CLRF PORTA
CLRF PORTB CLRF PORTC CLRF PORTD CLRF PORTE BSF STATUS,RP0 MOVLW H'06' MOVWF ADCON1 MOVLW H'FF' MOVWF TRISA CLRF TRISB MOVLW H'FF' MOVWF TRISC CLRF TRISD
MOVLW H'FF* MOVWF TRISE BCF STATUS,RPO CLRF PORTA CLRF PORTB CLRF PORTC CLRF PORTD CLRF PORTE CALL WELCOME CALL t2s
AGAIN BTFSSPORTE,0
GOTO $-1
MOVF PORTA, W
MOVWF TEMP
SUBLW B'01'
BTFSC STATUS,Z
GOTO BUS1DIR1
MOVF TEMP,W
SUBLW B'10'
BTFSC STATUS,Z
GOTO BUS1_DIR2
MOVF TEMP,W
SUBLW B'100'
BTFSC STATUS,Z
GOTO BUS2DIR1
MOVF TEMP, W
SUBLW B'1000'
BTFSC STATUS,Z
GOTO BUS2DIR2 GOTO AGAIN
BUS1JDIR1
CALL DISPLAYB1D1
BSF PORTCO
BCF PORTC,0
BTFSSPORTD,0
GOTO $-2
CALL WELCOME
GOTO AGAIN
BUS1_DIR2
CALL DISPLAYB1D2 BSF PORTC, 1 BCF PORTC, 1 BTFSSPORTD.O GOTO $-2
CALL WELCOME
GOTO AGAIN
.**********************
BUS2 DIR1
CALL DISPLAYJ32 Dl
BSF PORTC,2
BCF PORTC2
BTFSSPORTD,0
GOTO $-2
CALL WELCOME
GOTO AGAIN

BUS2DIR2
CALL DISPLAY B2 D2
BSF PORTC,3
BCF PORTC,3
BTFSSPORTD.O
GOTO $-2
CALL WELCOME
GOTO AGAIN

init_lcd
bcf PORTD,7
movlw h'38'
movwfPORTB
bsf PORTD,6
bcf PORTD,6
call t3ms
bcf PORTD,7
movlw h'Oc'
movwfPORTB
bsf PORTD,6
bcf PORTD,6
call t3ms
bcf PORTD.,7
movlw h'06'
movwfPORTB
bsf PORTD,6
bcf PORTD,6
call t3ms
return
9 ******
dried bcf PORTD ,7
movlw h'OT
movwfPORTB
bsf PORTD,6
bcf P0RTD,6 call tlms
return
wr_lcd
bsf PORTDJ movwfPORTB bsf PORTU6 bcf PORTD,6 call tlms return
bcf PORTDJ movlw h'80' movwfPORTB bsf PORTD,6 bcf PORTD,6 call tlms return
bcf PORTDJ movlw h'CO' movwfPORTB bsf PORTD,6 bcf PORTD,6 call tlms return
WELCOME
CALL initlcd CALL clrjcd CALL lineOl MOVLW 'W MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'E' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms
MOVLW 'L MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'C MOVWF PORTB BSF PORTD.6 BCF PORTD,6 CALL t3ms MOVLW 'O' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'M' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'E' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms RETURN
DISPLAYB1 _D 1
CALL line_01 CALL clrjcd MOVLW T MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'P' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'4' CALL TABLE
MOVWF PORTB BSF PORTD,6 BCF PORTD.6 CALL t3ms xMOVLW H'3' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'7' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW T MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'V MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'M' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW '(' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'S' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'F'
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW ')' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms
CALL line_02 MOVLW HT CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'O' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW ':' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'3' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'O' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms RETURN
DISPLAY_B1_D2
CALL lineOl CALL clrjcd MOVLW T
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'P' MOVWF PORTB BSF PORTD.6 BCF PORTD,6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD.6 BCF PORTD,6 CALL t3ms MOVLW H'4' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'3' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H7' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'E' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'K' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms
MOVLW 'M*
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW '('
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW 'S'
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW 'F'
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW ')'
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
CALL line_02
MOVLW H'l'
CALL TABLE
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW H'8'
CALL TABLE
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW ':'
MOVWF PORTB
BSF PORTD,6
BCF PORTD,6
CALL t3ms
MOVLW H'l'
CALL TABLE
MOVWF PORTB
BSF P0RTD.6 BCF P0RTD.6 CALL t3ms MOVLW H'O' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms RETURN
DISPLAYB2D1
CALL line 01 CALL clrjcd MOVLW A' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'S' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H*6' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'5' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'l' CALL TABLE MOVWF PORTB BSF PORTD.6 BCF PORTD,6
CALL t3ms MOVLW
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'K' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW T MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'M' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW '(' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'S' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW . 'F' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW ')' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms
CALL line_02 MOVLW H'l' CALL TABLE MOVWF PORTB BSF PORTD,6
BCF P0RTD.6 CALL t3ms MOVLW H'2' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW ':' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'4' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD.6 CALL t3ms MOVLW H'O' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms RETURN
DISPLAY_B2_D2
CALL lineOl CALL clrlcd MOVLW 'A' MOVWF PORTB BSF PORTD.6 BCF PORTD.6 CALL t3ms MOVLW 'S' MOVWF PORTB BSF PORTD.6 BCF PORTD.6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD.6 BCF PORTD.6 CALL t3ms MOVLW H'6' CALL TABLE
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'5' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'l' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW T MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'V MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'M' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW '(' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'S' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW 'F'
MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW ')' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms
CALL line_02 MOVLW H'O' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'3' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW ':' MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'2' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms MOVLW H'5' CALL TABLE MOVWF PORTB BSF PORTD,6 BCF PORTD,6 CALL t3ms RETURN
tlms movlw d'2' ;(1) Set loop cntl
movwf cnt 1 ms;(1) Save loop cnt 1
taillpl movlw d'249' ;(1)*2 Set loop cnt2
movwf cntSOOus ;(1)*2 Save loop cnt2
tmllp2nop ;(1)*249*2 Time adjust
nop ;(1)*249*2 Time adjust
deefsz cnt500us,f ;(1)*249*2 cnt500u-l=0 goto tmllp2 ;(2)*248*2 No, continue deefsz cntlms,f ;(1)*2 cntlm-1=0 goto tmllpl ;(2) No. Continue
return ;(2) Yes. Cnt end
9
t3ms MOVLW D'3' ;COUNT=3
MOVWF CNT_3ms ;//
CALL tlms ;lms DELAY
DECFSZ CNT_3ms,F ;COUNT= -1
GOTO $-2 " ;LOOP
RETURN ;lmsx3 = 3ms
tlOOmsMOVLW D'100' ;COUNT=100
MOVWF CNTJOOms ;//
CALL tlms ;lms DELAY
DECFSZ CNT_100ms,F;COUNT=-l
GOTO $-2 " ;LOOP
RETURN ; 1 ms x 100 = 100ms
t500msMOVLW D'5' ;COUNT =5
MOVWF . CNT_500ms ;//
CALL 1100ms " ; 100ms DELAY
DECFSZ CNT_500ms,F;COUNT=-l
GOTO $-2 " ;LOOP
RETURN ; 100ms x 5 = 500ms
5
t2s MOVLW D'20* ;COUNT=20
MOVWF CNT_2s ;//
CALL 1100ms; 100ms DELAY
DECFSZ CNT_2s,F ;COUNT=-l
GOTO $-2 " ;LOOP
RETURN ;100msx20 = 2s
Pcb layout of transmitter board
6. PCB LAYOUT
o o o o
Component layout of transmitter board
Component layout of transmitter board
6. COST ESTIMATION
COMPONENTS QTY RATE COST
PIC16F877A 1 170.00 170.00
LM555 1 8.00 8.00
1/4W RESISTOR 15 0.25 3.75
1W RESISTOR 3 1.00 3.00
BC547 2 2.50 5.00
BUZZER 1 30.00 30.00
LCD 1 200.00 200.00
12-0-12/1A TRANSFORMER 1 100.00 100.00
1N4007 2 1.00 2.00
4700MFD/30V CAPACITOR 1 25.00 25.00
10MFD/25V CAPACITOR 4 2.50 10.00
0.1 MFD DISC CAPACITOR 5 1.00 5.00
40PIN IC BASE 1 6.00 6.00
16PIN IC BASE 5 2.00 10.00
8PFN IC BASE 1 1.00 1.00
47K PRESET 3 10.00 30.00
LM7805 1 10.00 10.00
10MHz CRYSTAL 1 10.00 10.00
ASK MODULE
TXOl 2 400.00 800.00
RX04 1 500.00 500.00
PCB 2 300.00
WIRE lOMtr 5.00 50.00
IC BURNING 500.00
SOLDERING IRON (25W) 1 200.00 200.00
SOLDER & FLUX 1 50.00 50.00
EXTRA 300.00
TOTAL 5010.75
6. CONCLUSION
The AUTOMATIC BUS STATION ANNOUNCEMENT was designed and implemented successfully. The circuit was designed as per the specifications and the requirements. The working conditions and the various constraints were properly studied before going through the designing steps.
11. REFERENCE
Design with PIC Microcontrollers By John B. Peatman
microchip.com
national.com
fairchildsemi.com
Microchip
PIC16F87X
28/40-pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
¢ PIC16F873 ¢ PIC16F876
¢ PIC16F874 ¢ PIC16F877
Microcontroller Core Features:
High-performance RISC CPU Only 35 single word instructions to learn All single cycle instructions except for program branches which are two cycle Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM data memory Pinout compatible to the PIC16C73B/74B/76/77 Interrupt capability (up to 14 sources) Eight level deep hardware stack Direct, indirect and relative addressing modes Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code-protection Power saving SLEEP mode Selectable oscillator options Low-power, high-speed CMOS FLASH/EEPROM technology Fully static design
In-Circuit Serial Programming„¢ (ICSP) via two pins
Single 5V In-Circuit Serial Programming capability In-Circuit Debugging via two pins Processor read/write access to program memory Wide operating voltage range: 2.0V to 5.5V High Sink/Source Current: 25 mA Commercial and Industrial temperature ranges Low-power consumption:
- < 2 mA typical @ 5V, 4 MHz
- 20 nA typical @ 3V, 32 kHz
- < 1 |iA typical standby current
Pin Diagram
PDIP
MCLR/Vpp/THV RA0/AN0 RA1/AN1 RA2/AN2/VREF-RA3/AN3/VREF+ RA4rT0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 Vdd Vss
OSC1/CLKIN OSC2/CLKOUT RCOmOSO/TICKI RC1/T10SI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1
Peripheral Features:
¢ TimerO: 8-bit timer/counter with 8-bit prescaler
¢ Timerl: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock
¢ Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
¢ Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
¢ 10-bit multi-channel Analog-to-Digital converter
¢ Synchronous Serial Port (SSP) with SPI„¢ (Master Mode) and l2C„¢ (Master/Slave)
¢ Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection
¢ Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only)
¢ Brown-out detection circuitry for Brown-out Reset (BOR)
PIC16F87X
13.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 13-2 lists byte-oriented, bit-ori¬ented, and literal and control operations. Table 13-1 shows the opcode field descriptions.
For byte-oriented instructions, 'f represents a file reg¬ister designator and'd' represents a destination desig¬nator. The file register designator specifies which file register is to be used by the instruction.
The destination designator specifies where the result of the operation is to be placed. If'd' is zero, the result is placed in the W register. If'd' is one, the result is placed in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f represents the number of the file in which the bit is located.
For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.
OPCODE FIELD DESCRIPTIONS execution time is 1 us. If a conditional test is true or the program counter is changed as a result of an instruc¬tion, the instruction execution time is 2 (is.
Table 13-2 lists the instructions recognized by the MPASM assembler.
Figure 13-1 shows the general formats that the instruc¬tions can have.
Note: To maintain upward compatibility with future PIC16CXX products, do not use the OPTION and TRIS instructions.
All examples use the following format to represent a hexadecimal number:
Oxhh
where h signifies a hexadecimal digit.
GENERAL FORMAT FOR INSTRUCTIONS
OPCODE
Byte-oriented file register operations
13 8 7 6
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
OPCODE
Bit-oriented file register operations
13 10 9 7 6
b(BIT#) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
8 7
k (literal)
General 13
OPCODE
k = 8-bit immediate value
k (literal)
CALL and GOTO instructions only
13 11 10
OPCODE
The instruction set is highly orthogonal and is grouped into three basic categories:
¢ Byte-oriented operations
¢ Bit-oriented operations
¢ Literal and control operations
All instructions are executed within one single instruc¬tion cycle, unless a conditional test is true or the pro¬gram counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruc¬tion cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz. the normal instruction k = 11-bit immediate value
A description of each instruction is available in the PICmicro„¢ Mid-Range Reference Manual, (DS33023).
© 1999 Microchip Technology Inc.
DS30292B-page 137
PIC16F87X
TABLE 13-2: PIC16CXXX INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d Add W and f 1 00 0111 df ff f f f f CDC.Z 1,2
ANDWF f, d AND W with f 1 00 0101 df f f ff f f Z 1,2
CLRF f Clear f 1 00 0001 If f f f f ff Z 2
CLRW - Clear W 1 00 0001 Oxxx XX XX z
COMF f, d Complement f 1 00 1001 df ff f f f f z 1,2
DECF f, d Decrement f 1 00 0011 df ff f f f f z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 df ff ff f f 1,2,3
INCF f, d Increment f 1 00 1010 df ff f f f f z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 df ff f f f f 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 df f f f f f f z 1,2
.MOVF f, d Move f 1 00 1000 dfff f f f f z 1,2
MOVWF f Move W to f 1 00 ¦ 0000 Iff f ff f f
NOP No Operation 1 00 0000 OxxO 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff f f f f C 1,2
RRF f. d Rotate Right f through Carry 1 00 1100 dfff ff f f C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ff ff CDC.Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ff ff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff f f ff z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bf f f f f f f 1,2
BSF f, b Bit Set f 1 01 Olbb bff f f f f f 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 lObb bff f f f f f 3
BTFSS f, b Bit Test f. Skip if Set 1 (2) 01 llbb bf ff f f f f 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 lllx kkkk kkkk C.DC.Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk z
CALL k Call subroutine 2 10 Okkk kkkk kkkk
CLRWDT Clear Watchdog Timer 1 00 0000 0110 0100 TO.PD
GOTO k Go to address 2 10 lkkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 OOxx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 Olxx kkkk kkkk
RETURN - Return from Subroutine 2 00 ¦ 0000 0000 1000
SLEEP - Go into standby mode 1 00 0000 0110 0011 TO.PD
SUBLW k Subtract W from literal 1 11 HOx kkkk kkkk C.DCZ
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, I), the value used will be that value present on the pins themselves. For example, if the data latch is 'V for a pin configured as input and is driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMRO register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the TimerO Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro„¢ Mid-Range MCU Family
Reference Manual (DS33023).
DS30292B-page 138
© 1999 Microchip Technology Inc.
HDLTEK
HT12D/HT12F 212 Series of Decoders
Features
¢ Operating voltage: 2.4V-12V
¢ Low power and high noise immunity CMOS technology
¢ Low standby current
¢ Capable of decoding 12 bits of information
¢ Binary address setting
¢ Received codes are checked 3 times
¢ Address/Data number combination
- HT12D: 8 address bits and 4 data bits
- HT12F: 12 address bits only
¢ Built-in oscillator needs only 5% resistor
¢ Valid transmission indicator
¢ Easy interface with an RF or an infrared transmission medium
¢ Minimal external components
¢ Pair with Holtek's 212 series of encoders
¢ 18-pin DIP, 20-pin SOP package
Applications
¢ Burglar alarm system
¢ Smoke and fire alarm system
¢ Garage door controllers
¢ Car door controllers
¢ Car alarm system
¢ Security system
¢ Cordless telephones
¢ Other remote control systems
General Description
The 212 decoders are a series of CMOS LSIs for remote control system applications. They are paired with Holtek's 212 series of encoders (refer to the encoder/de¬coder cross reference table). For proper operation, a pair of encoder/decoder with the same number of ad¬dresses and data format should be chosen.
The decoders receive serial addresses and data from a programmed 212 series of encoders that are transmitted by a carrier using an RF or an IR transmission medium. They compare the serial input data three times continu-ously with their local addresses. If no error or un¬matched codes are found, the input data codes are decoded and then transferred to the output pins. The VT pin also goes high to indicate a valid transmission.
The 212 series of decoders are capable of decoding informations that consist of N bits of address and 12-N bits of data. Of this series, the HT12D is arranged to pro-vide 8 address bits and 4 data bits, and HT12F is used to decode 12 bits of address information.
Selection Table
^~\^Function Part No. Address No. Data VT Oscillator Trigger Package

No. Type



HT12D 8 4 L RC oscillator DIN active "Hi" 18DIP, 20SOP
HT12F 12 0 ” RC oscillator DIN active "Hi" 18DIP, 20SOP
Notes: Data type: L stands for latch type data output. VT can be used as a momentary data output.
Block Diagram
OSC2 0SC1
-„¢o~-
4
Oscillator
Divider
Data Shift Register
Latch Circuit
o
i Data
DIN 0”*¢
Buffer
Data Detector [
Sync. Detector
Comparator
Comparator
Control Logic
Transmission Gate Circuit
Buffer ”VT
1 1
Address VDD VSS
Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment
8-Address 4-Data
8-Address 4-Data
12-Address 0-Data
12-Address 0-Data
AOC 1 A1 C 2 A2C 3 A3C 4 A4C 5 A5C 6 A6C 7 A7C 8 VSSC 9
18 7J VDD 17 VT 16 7JOSC1 15 UOSC2 14 TJ DIN 13 D11 12 D10 11 D9 10 D8
NCC 1 AOC 2 A1 C 3 A2C 4 A3 C 5 A4C 6 A5C 7 A6C 8 A7C 9 VSSC 10
XT
20 "JNC 19 VDD 18 VT 17 7JOSC1 16 CIOSC2 15 DIN
D11 7JD10
D9 HD8
AO C 1 A1 C 2 A2C 3 A3 C 4 A4 C 5 A5 C 6 A6 C 7 A7C 8 VSSC 9
ClVDD VT
16pOSC1
OSC2
DIN
A11
A10
A9
A8
NCC 1 AOC 2 A1 C 3 A2C 4 A3 C 5 A4C 6 A5C 7 A6C 8 A7C 9 VSSC 10
20 NC 19 ClVDD 18 ClVT 17 DOSC1 16 OSC2 15 DIN 14 DA11
13C1A10
A9
A8
HT12D -18 DIP-A
HT12D - 20 SOP-A
HT12F -18 DIP-A
HT12F - 20 SOP-A
Pin Description
Pin Name I/O Internal Connection Description
A0-A11 (HT12F) I NMOS Transmission Gate Input pins for address A0-A11 setting
These pins can be externally set to VSS or left open.
A0~A7(HT12D)

Input pins for address A0-A7 setting
These pins can be externally set to VSS or left open.
D8-D11 (HT12D) O CMOS OUT Output data pins, power-on state is low.
DIN I CMOS IN Serial data input pin
VT O CMOS OUT Valid transmission, active high
OSC1 I Oscillator Oscillator input pin
OSC2 0 Oscillator Oscillator output pin
VSS ” ” Negative power supply, ground
VDD ” ” Positive power supply
HDLTEKnr^ HT12A/HT12E
212 Series of Encoders
¢ Operating voltage
- 2.4V-5V for the HT12A
- 2.4V-12V for the HT12E
¢ Low power and high noise immunity CMOS technology
¢ Low standby current: O.luA (typ.) at VDD=5V
¢ HT12A with a 38kHz carrier for infrared transmission medium
Applications
¢ Burglar alarm system
¢ Smoke and fire alarm system
¢ Garage door controllers
¢ Car door controllers
General Description
The 212 encoders are a series of CMOS LSIs for remote control system applications. They are capable of encoding information which consists of N address bits and 12-N data bits. Each ad-dress/data input can be set to one of the two logic states. The programmed addresses/data are transmitted together with the header bits
Features
¢ Minimum transmission word
- Four words for the HT12E
- One word for the HT12A
¢ Built-in oscillator needs only 5% resistor
¢ Data code has positive polarity
¢ Minimal external components . HT12A/E: 18-pin DIP/20-pin SOP package
¢ Car alarm system
¢ Security system
¢ Cordless telephones
¢ Other remote control systems
via an RF or an infrared transmission medium upon receipt of a trigger signal. The capability to select a TE trigger on the HT12E or a DATA trigger on the HT12A further enhances the ap-plication flexibility of the 212 series of encoders. The HT12A additionally provides a 38kHz car¬rier for infrared systems.
Selection Table
^"\Function Part No/~"\^ Address No. Address/ Data No. Data No. Oscillator Trigger Package Carrier Output Negative Polarity
HT12A 8 0 4 455kHz resonator D8-D11 18 DIP 20 SOP 38kHz No
HT12E 8 4 0 RC oscillator TE 18 DIP
20 SOP No No
Note: Address/Data represents pins that can be address or data according to the decoder require¬ment.
1 April 11, 2000
Block Diagram
TE trigger
HT12E
OSC2 OSC1
3T£
TE0”*\ Oscillator
-3 Divider
Data Select I^AQQUT & Buffer '
AOO”> A7 0”*
12 Transmission Gate Circuit
+12 Counters 1 of 12 Decoder
Binary Detector
Sync. Circuit
4
AD8 AD11
4 1-
VDD VSS
DATA trigger
HT12A
X2 X1
3Zt
Oscillator
+576 Divider
Data Select L_^oD0UT & Buffer '
L/MBO-
AP0~7* A7<^>->
D8 ¦
12 Transmission Gate Circuit
¢ D11
+12 Counters 1 of 12 Decoder
Binary Detector
Sync. Circuit
4 i
VDD VSS
Note: The address data pins are available in various combinations (refer to the address/data table).
2
April 11,2000
PATH DESTINATION LIFE ULTIMATE TRUTH & TRUE SALVATION IS DIVINE MOTHER MAA API SHAKTI THE SUPREME ENGRY SHREE ADHYASHAKTI MAHAKAALI MAHALAXMI MAHASARASWAT1 PRASANNA
Electronics Projects & Kits - Product Design & Development - Project Consultancy & Solutions
ASK RECEIVER - RX 02 - ASK
GENERAL DESCRIPTION :-
The RX 02 - ASK is an ASK Hybrid receiver module. It is a effective low cost solution for using 433 MHz.
PIN DISCRETION
Pin Description:
> a a < <uuo 22:2:0 n > > 2:
HI O w *j n H H U
> >
RX 02 - ASK
APLUS INDIA
FEATURES :-
¢ Circuit Shape : L / C
¢ Receiver Frequency : 433 MHz
¢ Typical Sensitivity : 105 Dbm
¢ Supply Current : 3.5 mA
¢ IF Frequency : 1MHz
¢ Low Power Consumption
¢ Easy For Application
¢ Operating Temperature Range : -10 degree C ~ + 60 degree C
¢ Operating Voltage : 5V
APPLICATIONS :-
¢ Car Security System
¢ Wireless Security System
¢ Sensor Reporting
¢ Automation System
¢ Remote Keyless Entry
ELECTRICAL CHARACTERISTICS
Vet Supply Voltage 5 VDC
Is Supply Current 3.S 4.5 mA
FR Rent-iver Frequency 315/434 MHz
RF Sensitivity(Vc<=5V IKbpj Data Rite} 105 (IBm
Max Data Kate 300 lk 3k Kbit/s
Voh High Level Output (i-30uA.) 0.7VCC VDC
VOL Low Level Output (I = 30uA) 0.3Vct VDC
Turn On Time(Vec off-Turn on) 25 ms
I OP Operating Temperature Range -10 60
Output Duty 40 60 %
4PLUS INDIA
ASK TRANSMITTER MODULE - TX 01 - ASK
GENERAL DISCRETION :-
The TX 01 - ASK is an ASK Hybrid transmitter module. TX 01 - ASK is designed by the saw resonator, with and effective low cost, small size and simple to use for designing.
FEATURES :-
¢ Frequency Range : 433.92 MHz
¢ Supply Voltage : 3V to 6V
¢ Output Power : 4 ~ 12 dbm
¢ Circuit Shape : Saw
APPLICATIONS :-
¢ Wireless Security Systems
¢ Car Alarm Systems
¢ Remote Controls
¢ Sensor Reporting
Electronics Projects & Kits - Product Design & Development - Project Consultancy & Solutions

i want full block diagram and circuit diagram of the project "AUTOMATIC BUS ANNOUNCEMENT SYSTEM"..its urjent plz sent it fast.

The circuit diagram is present here:
http://scribddoc/37202401/Automatic-Bus-Station-Announcement-System

is this software project or hardware project?

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please tell hardware projects for ece latest projects

Wireless communication can be defined as transfer of information between two or more points without using wires or cables. There are different wireless technologies such as RFID, IR, GPS, Bluetooth, and WI-FI, etc. In olden days location announcement was done with the help of speakers, but now it is developed by using IVRS in railways stations. Nowadays bus location can be found with the help of Geo Positioning satellites.

This bus location announcement system is very helpful for people who are illiterates and new to cities. This system can be applied in different areas like transport companies, public trains, private travels, government travel agencies, service organizations, etc.

GPS Involvement in Finding Bus Location

Global positioning system is a satellite-based navigation system used to locate positions anywhere on earth. This kind of technology can be used in various areas like military, commercial usage and civil services all over the world. GPS can be used for these purposes: trilateration, perfect timing, positioning of satellites and error connection. Here is the general example describing the use of GPS: