why we use 8085 processor in microprocessor based alt synchronisation ....etc

[:=Read Full Message Here=:]

Abstract
The effect of microprocessor pipeline depth on performance is considered. It is found that pipeline depth is a tradeoff between various factors, including the degree of superscalar processing, fraction of pipeline hazards, the fabrication technology of the processor, and the processor workload. The degree of instruction level parallelism decreases the optimal pipeline depth, while the lack of pipeline stalls increases the optimal pipeline depth. As we increase pipeline depth, there is a competition between greater pipeline throughput ....etc

[:=Read Full Message Here=:]

ABSTRACT
The manual method of
synchronization demands a skilled operator and the method is suitable
for no load operation or normal frequency condition. under emergency
condition such as lowering of frequency or synchronizing of large
machines a very fast action is needed, which may not be possible for a
human operator. Thus there is a need of autosynchroniser in a power
station or in an industrial establishment where generator are employed.
This paper describes a m ....etc

[:=Read Full Message Here=:]

Electrical load on power system varies and it never be constant. To economically meet the requirement of variable load and to assure continuous supply the number of generator unit connected to the system bus bar are varied suitably.

The synchronization requires fulfillment of various conditions like
(1) Same phase sequence
(2) Equality of frequency and voltage between incoming machine and bus.

At present the synchronization is done manually by using conventional analog instruments. The ....etc

[:=Read Full Message Here=:]

class A extends Thread
{
public void run()
{
try
{
for(int i=0;i<=15;i++)
{
System.out.println(In thread A\t+i);
if(i==10)
sleep(100);
}
}
catch(Exception e)
{
System.out.println(Exception+e);
}
}
}

class B extends Thread
{
public void run()
{
for(int j=0;j<=15;j++)
{
System.out.println(In thread B\t+j);
if(j==0) yield();
}
}
}

class C extends Thread
{
public void run()
{
for(int k=0;k<=15;k++)
{
System.out.println(In thread C\t+k);
if(k= ....etc

[:=Read Full Message Here=:]

Intel?s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel Architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a micro architecture pers ....etc

[:=Read Full Message Here=:]

Electronic motor speed controllers first appeared during the 1980s and many were based on dedicated integrated circuits originally designed as a servo controllers. However, with suitable circuit modifications, these ICs could also be used as the basis for a simple electronic speed controller. Since that time a number of significant events have occurred:- ? The workhorses of many older electronic motor speed controller designs, the tried and tested ZN409 and ZN419 servo amplifier ICs, have been made obsolete. ? MOSFET technology has developed an ....etc

[:=Read Full Message Here=:]

Abstract Test card for color TV is a widely used method to evaluate the quality of a TV set directly. We have made a test signal generator (which can also generate synchronizing (abbreviated to sync hereafter) signals) mainly based on microprocessor Z-80. Taking the advantage of microprocessor programming, combining with the technique of microprocessor, digital circuits and analogue devices, we use software as far as possible to generate signals directly or to simplify the controlling circuits. Those signals, such as composite sync signal, bla ....etc

[:=Read Full Message Here=:]

Cell is a microprocessor architecture jointly developed by Sony Computer Entertainment, Toshiba, and IBM, an alliance known as STI. Each SPE is composed of a Synergistic Processing Unit, SPU, and a Memory Flow Controller, MFC (DMA, MMU, and bus interface).The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a budget reported by Sony as approaching US$400 million. Cell is shorthand for Cell Broadband Engine Architecture, commonly abbrevi ....etc

[:=Read Full Message Here=:]

RAPTOR MICROPROCESSOR

Abstract:- The Raptor-16 is a 16-bit embedded microprocessor that boasts the following features

* Full CISC Architecture
* Extremely Powerful Instruction Set
* 12 Base Instructions with 44,961 Combinations
* 4 spare Instruction slots for Signed & Unsigned Divide & Multiply
* Variable Length Instructions (1, 2 or 3 words)
* Special Quick Instructions for Extremely Compact Code
* 12 Addressing Modes
* 16 Registers
* 4 Condition Codes
* 16 Branch Conditions
* Direct ....etc

[:=Read Full Message Here=:]