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Title: Interfacing the Standard Parallel Port
Page Link: Interfacing the Standard Parallel Port -
Posted By: seminar surveyer
Created at: Monday 18th of October 2010 12:26:24 PM
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Introduction

The Parallel Port is the most commonly used port for interfacing home made projects. This port will allow the input of up to 9 bits or the output of 12 bits at any one given time, thus requiring minimal external circuitry to implement many simpler tasks. The port is composed of 4 control lines, 5 status lines and 8 data lines. It's found commonly on the back of your PC as a D-Type 25 Pin female connector. There may also be a D-Type 25 pin male connector. This will be a serial RS-232 port and th ....etc

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Title: Three Port Series Resonant DC-AC converter
Page Link: Three Port Series Resonant DC-AC converter -
Posted By: project report helper
Created at: Saturday 09th of October 2010 03:39:49 PM
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Three Port Series Resonant DC-AC converter

By
Karuppiah.S
Mohan Kumar.A
Shreeeram.G.R


Why This Project?

Fuel Cell
Electric Car
Failure of AC transformer
To Interface Renewable Energy sources With Bi-directional Load & Energy Storage Ports.


....etc

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Title: Online Port Scanner
Page Link: Online Port Scanner -
Posted By: project topics
Created at: Thursday 22nd of April 2010 03:01:43 AM
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Online Port Scanner

Online Port Scanner is a web user control in C# NET 2. The web user control will later be placed within an ASP.NET page. The purpose of the control is to offer admin a control panel where he can add port like http 80, FTP 21 and so on. Next will be to offer user a form where he/she can start a scan towards own firewall or computer. The purpose of the test is to display ports that are open or exposed to threats.

The port scanner will also have a statistics module that show what ports are most often found open. How many ....etc

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Title: DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO FOR EMBEDDED APPLICATIONS
Page Link: DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO FOR EMBEDDED APPLICATIONS -
Posted By: computer science crazy
Created at: Thursday 17th of September 2009 04:31:49 AM
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DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO FOR EMBEDDED APPLICATIONS

A FIFO is used as a First In-First Out memory buffer between two asynchronous systems with simultaneous write and read access to and from the FIFO, these accesses being independent of one another. Data written into a FIFO is sequentially read out in a pipelined manner, such that the first data written into a FIFO will be the first data read out of the FIFO.

FIFO status flag outputs are a function of the comparison of the respective write and read pointers. A FIFO w ....etc

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Title: DUAL PORT FIFO
Page Link: DUAL PORT FIFO -
Posted By: computer science crazy
Created at: Friday 18th of September 2009 12:26:23 AM
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DUAL PORT FIFO

Abstract:- The dual port FIFO is now a standard building block in most designs, especially in the area of communications where it is used frequently for packet work. Although very useful in its basic form, the standard FIFO does lack two attributes; autonomy and cascadability. Unfortunately you cannot simply connect two FIFOâ„¢s together, as shown below, and expect them to automatically transfer data ....etc

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Title: Real Time Port Scan Detection for Internet Backbone
Page Link: Real Time Port Scan Detection for Internet Backbone -
Posted By: project topics
Created at: Thursday 22nd of April 2010 02:32:22 AM
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Real Time Port Scan Detection for Internet Backbone

Malware of many different varieties continue to spread through todayâ„¢s Internet at an alarming rate and volume. Port scanning, along with email and web page phishing, are the major channels of such propagation. This perpetual and unwanted scanning traffic is often aimed at discovering and infecting vulnerable hosts with viruses, leading eventually to botnets and criminal activities To understand, detect and eliminate such traffic is a vital part of enhancing Internet security.

Here ....etc

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Title: A HIGH SPEED DISTRIBUTED FIFO SCHEME FOR MANAGING INTERCONNECTS
Page Link: A HIGH SPEED DISTRIBUTED FIFO SCHEME FOR MANAGING INTERCONNECTS -
Posted By: computer science crazy
Created at: Friday 18th of September 2009 12:25:12 AM
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A HIGH SPEED DISTRIBUTED FIFO SCHEME FOR MANAGING INTERCONNECTS

Abstract:- Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as well as the transistors. Scaling trends allow for complete systems to be built on a single chip (SoC), but they require long interconnects for global signals and clock distribution networks. The parasitic of these global interconnects make efficient and high-performance operation difficult. On-chip communicati ....etc

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Title: Parallel Port Interface
Page Link: Parallel Port Interface -
Posted By: mechanical wiki
Created at: Friday 04th of September 2009 02:14:57 AM
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Parallel Port Interface

The main components are 74LS367 Buffer IC and Case, Wire, Sockests, 18 Pin Socket (For Output), 25 Pin Connector (For Parallel Port), Ribben Cable

http://pptpdf.net/subcategory.php?categ=unknown&categ_id=1&/Project%20Reports/Electrical-Electronics-Apllied_Electronics-Instrumentation/project%20list1 ....etc

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Title: multichannel uart controller based on fifo technique and fpga ppt
Page Link: multichannel uart controller based on fifo technique and fpga ppt -
Posted By:
Created at: Thursday 03rd of January 2013 11:51:03 AM
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....etc

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Title: Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
Page Link: Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA -
Posted By: projectsofme
Created at: Wednesday 13th of October 2010 08:01:24 PM
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This article is presented by:
Shouqian Yu
Lili Yi
Weihai Chen
Zhaojin Wen
Implementation of a Multi-channel UART
Controller Based on FIFO Technique and FPGA


Abstract:
To meet modern complex control systems communication demands, the paper presents a multi-channel UART controller based on FIFO(First In First Out) technique and FPGA(Field Programmable Gate Array). The paper presents design method of asynchronous FIFO and structure o ....etc

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