01-03-2017, 03:08 PM
Matrix multiplication design using VHDL and Xilinx Core Generator
The VHDL code for Matrix multiplication is presented. This project aims to develop and implement a synthesizable matrix multiplier core, which is capable of performing matrix calculations for 32x32 size matrices.
Each component of the matrices is a 16-bit unsigned integer. The kernel is implemented in Xilinx FPGA Spartan-6 XC6SLX45-CSG324-3. Both behavior and post-route verification are completed. The simulated result is matched accurately to the result of the Matlab implementation.
![[Image: MUlt1.jpg]](https://2.bp.blogspot.com/-HzYrhX0UPwU/WBrMTiGmj9I/AAAAAAAAEoE/9irGJN45V1kcppHCubEdbGsf2W9ZcksjwCLcB/s640/MUlt1.jpg)
Block Diagram of the Design Core
The design core is based on the matrix addition reference design, whose input and output buffers are generated by Xilinx Core Generator to store input and output data. The main job is the block for calculating matrix multiplication.
The VHDL code for Matrix multiplication is presented. This project aims to develop and implement a synthesizable matrix multiplier core, which is capable of performing matrix calculations for 32x32 size matrices.
Each component of the matrices is a 16-bit unsigned integer. The kernel is implemented in Xilinx FPGA Spartan-6 XC6SLX45-CSG324-3. Both behavior and post-route verification are completed. The simulated result is matched accurately to the result of the Matlab implementation.
Block Diagram of the Design Core
The design core is based on the matrix addition reference design, whose input and output buffers are generated by Xilinx Core Generator to store input and output data. The main job is the block for calculating matrix multiplication.
