vhdl implementation of BAUGH WOLLEY MULTIPLIER

vhdl code for 4 bit baugh wooley multiplier

Abstract:

This Paper presents the work on implementation of Baugh-Wooley multiplier based on soft-core processor. MicroBlaze soft core is high performance embedded soft core processor developed by XILINX Company. This soft core enjoys high configurability and allows designer to make proper choice based on his own design requirements to build his own hardware platform. Custom hardware of power optimized Baugh-Wooley signed multiplier is interface with MicroBlaze soft core processor. The major objective for using hardware for realizing Baugh-Wooley multiplier is to utilize hardware for realizing fast and efficient processing capacity.

INTRODUCTION
Multipliers play an important role in today‟s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of
layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact implementation.The common multiplication method is “add and shift” algorithm. In parallel multipliers number of partial products to be added is the main parameter that determines the performance of the multiplier. To achieve speed improvements Baugh-Wooley algorithm can be used. This multiplier subsystem is commonly implemented using an embedded processor combined with specific hardware. Field programmable gate arrays (FPGAs) provide designers with the ability to quickly create hardware of circuits. Increases in FPGA configurable logic capacity and decreasing FPGA costs have enabled designers to more readily incorporate FPGAs in their designs. While FPGAs with soft processor cores provide designers with increased flexibility. Reconfigurable logic devices, such as field programmable gate arrays (FPGAs), have been very effective to implement dedicated multiplier architectures . Over the last few years, the huge increase in FPGA features made possible the implementation of a whole system in a single device: processor, peripherals, memories and so on. Nowadays, it is feasible to implement on an FPGA an entire multiplication algorithm based
on a soft-core processor (SCP), which also includes multiplier cores for hardware acceleration . There are a several soft core processors that are commonly used in SOC applications like PowerPC NIOS3 , MicroBlaze , and free or open cores that may be used without the need to acquire a license, like LEON3 [6]. The main advantage of these processors are that they are usually well tested and optimized for a specific target hardware and provide a complete set of CAD tools to make the SOC design an easier process. For example, MicroBlaze from Xilinx is well integrated with the development platform from the same foundry, which leads to highly optimized designs at the cost of being bound to a particular technology (Xilinx Spartan
and Virtex FPGA families ) and a concrete set of tools (Xilinx ISE and EDK