Verilog source code for traffic light controller that can use at 3 and 4 junctionskimeyaacob[at]yahoo.com" class="mycode_email

DESIGN of traffic light controller using Verilog

DESIGN of traffic light controller using Verilog

AIM:
Design of traffic light controller using Verilog.
Device is required:
· Personal computer.
· Xilinx ISE software.
THEORY:
Consider the controller for a traffic light at the intersection of four roads. Consider the P1, P2, P3, and P4 as four roads and the PL as pedestrians Road consists of the following steps.
Green = 10011,
Yellow = 01000,
Red = 00100.
Pedestrian following two
Green = 00000000
Red = 1111
First road P1 green and all other road P2, P3, P4, and PL red. After some delay, P1, this turn to yellow and then red light at P2 green. After delaying P2 refer to yellow and then a red signal on a P3 green.Then P3 is changed to yellow and then red. Similarly, P4, the yellow has turned green and then red. A pedestrian Light PL green after the delay. P1 is in green again and the program will continue.
PROGRAM:
Traffic module (CLK, reset, P1, P2, P3, P4, PL);
input CLK;
input reset;
power [4: 0], page 1;
power [4: 0] p2;
power [4: 0] p3;
power [4: 0] 4;
power [3: 0] p1;
Reg [4: 0] p1;
Reg [4: 0] p2;
Reg [4: 0] p3;
Reg [4: 0] 4;
Reg [3: 0] PL;
Reg [4: 0] cur;
always @ (Posedge CLK or negedge reset)
Start
If (1'b0 == reset) begin
P1 = 5'b00100 <;
P2 = 5'b00100 <;
P3 < 5'b00100; =
P4 < 5'b00100; =
PL < = 4'b01111;
SIG = 6'b000000 <;
The end
else begin
SIG SIG + = 1 <;
case (SIG [4: 0])
6'b000000: start
P1 = 5'b10011 <; Path 1 green
P2 = 5'b00100 <; All other ways are red
P3 < 5'b00100; =
P4 < 5'b00100; =
PL < = 4'b1111;
The end
6'b000100: start
P1 = 5'b01000 <; Path 1 yellow
P2 = 5'b00100 <; All other ways are red
P3 < 5'b00100; =
P4 < 5'b00100; =
P1 = 4'b1111 <;
The end
6'b001000: start
P1 = 5'b00100 <; Path1 Red
P2 = 5'b10011 <; path2 Green
P3 < 5'b00100; = All other ways are red
P4 < 5'b00100; =
PL < = 4'b1111;
The end
6'b001100: start
P1 = 5'b00100 <;
P2 = 5'b01000 <; path2 yellow
P3 < 5'b00100; = All other ways are red
P4 < 5'b00100; =
PL < = 4'b1111;
The end
6'b010000: start
P1 = 5'b00100 <;
P2 = 5'b00100 <;
P3 < 5'b10011; = path3 is green
P4 < 5'b00100; = All other ways are red
P1 = 4'b1111 <;
The end
6'b010100: start
P1 = 5'b00100 <;
P2 = 5'b00100 <;
P3 < 5'b01000; = path3 is yellow
P4 < 5'b00100; = all other way Red
PL < = 4'b1111;
The end
6'b011000: start
P1 = 5'b00100 <;
P2 = 5'b00100 <;
P3 < 5'b00100; = all other way Red
P4 < 5'b10011; = path4 yellow
P1 = 4'b1111 <;
The end
6'b100000: start
P1 = 5'b00100 <; All other ways are red
P2 = 5'b00100 <;
P3 < 5'b00100; =
P4 < 5'b00100; =
P1 = 4'b0000 <; The pedestrian green
6'b100100: SIG < = 6'b000000
default: start
The end
end case
The end
The end
End Module
THE RESULT:
Thus, traffic light controller using Verilog module is designed.