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INTRODUCTION
When an active process requires any external device for its proper execution, it makes a request for that device through some means. If that particular device is free and readily available for its use, the process will go on normally and there will be no delay in the execution of that particular requesting process. If in case the device requested by the process is temporarily unavailable for its use then, it introduces a delay in the execution of the process, thus increasing the number of clock cycles required for its execution.
A single process may request for its corresponding real device at a time or several requests may be made by several different processes for their particular external devices concurrently. The latter is a worst case wherein many processes may be left unserved resulting in ambiguity or may be served after a certain delay when the device becomes available for its use.
To avoid such a delay the software version/simulators of the real devices can be developed and made use of as the emulators for the real/external devices whenever they are unavailable. Even though such simulators are not fully capable of serving the full functionality as the real device for a process, it helps in reducing the delay and thus aids in faster execution of the process. These simulators will be opened on the serial channels of the computer and routed appropriately.
Here a question arises. What if the serial channel of the corresponding simulator is also unavailable? The flexibility here is that the simulator of any real device can be opened on any of the serial channels/ports in the computer. This results in no ambiguities, no delays even if many active processes requests for the real or simulators at the same time, as we can use any number of serial ports, creating them virtually, if not available physically in a computer.
To achieve such a scheme a routing and switching logic is required to select between various external devices or their simulators based on their availability. The external or simulator thus selected must be routed to the appropriate channel at the output side on which the request was made by the requesting process. To achieve such interface, a routing logic must be developed. To develop such a logical interface we make use of Complex Programmable Logic Device (CPLD) which will be programmed as per the logic required.
1.1 Scope
Stimulation for the project work “Simulator Switching Card" is due to its tremendous scope in the applications where time is an important constraint and any sort of delay in servicing the requesting processes is not accepted.
The project is aimed at providing instant service to any active process that requests for a device for its proper execution.
Programmable logic devices can be used to control and route the requested real device or its simulator to the corresponding process by which the request was made.
1.2 Objective of Study
Main objective is to cater the requirement of immediate servicing of the requests made by the active processes for which time is a rigid constraint.
To understand the capabilities and functioning of the Programmable Logic Devices, various interfaces that can be used to interface such a logic device to another data terminal and the different methods that can be used to control the functioning of the device.
1.3 Outcome of Project
If the requested real data is not currently available to service the process, then the simulated data will be instantly available for the requesting process for its use. Hence the process will be serviced in a reduced cycle time.
1.4 Development Specification
Platform : Windows XP, Windows 7
Language : VHDL
Package : XILINX
Library : CoolRunner-II
Simulator : Modelsim
1.5 Motivation
The motivation for developing this card is the requirement of low cost, high speed switching between the various peripheral devices. This is extremely important in military applications where the selection and routing of the requested devices must be done instantly. The processes cannot be made to wait in such critical cases. Hence a highly robust medium which is capable of operating over a wide range, able to serve any number of active processes and provides a provision to switch to the manual operation in case of the module failure must be developed to avoid uncertainties in applications were time is an important constraint .

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Abstract
In most cases, the real/external devices may be unavailable for a process for its use. In such cases a virtual environment or their simulator can serve the functionality of the real system. Although such a simulator cannot provide the full functionality as the external device, it may be helpful in avoiding the delay of the execution of a process requesting a particular real device and thus reduce the cycle time. Many such simulators/real versions may be required by each different process concurrently. In such a scenario, a scheme has to be developed such that the real or simulator can be used to carry out the process in a reduced time. Logical interface has to be developed to cater the requirement of using real or simulators. To achieve such interface, we make use of Complex Programmable Logic Device(CPLD) which will be interfaced to the serial computer ports of a CPU. The final output of the CPLD will be the required simulator or real data on the corresponding channel.
Keywords— Complex Programmable Logic Device, GPIO lines, transceivers, relays.
I. INTRODUCTION
When an active process requires any external device for its proper execution, it makes a request for that device through some means. If that particular device is free and readily available for its use, the process will go on normally and there will be no delay in the execution of that particular process. If in case the device requested by the process is temporarily unavailable for its use then, it introduces a delay in the execution of the process, thus increasing the number of clock cycles required for its execution.
A single process may request for its corresponding real device at a time or several requests may be made by several different processes for their particular external devices concurrently. This is a worst case wherein many processes may be left unserved resulting in ambiguity or may be served after a certain delay when the device becomes available for its use.
To avoid such a delay the software version/simulators of the real devices can be developed and made use of as the emulators for the real/external devices whenever they are unavailable. Even though such simulators are not fully capable of serving the full functionality as the real device for a process, it helps in reducing the delay and thus aids in faster
execution of the process. These simulators will be opened on the serial channels of the computer and routed appropriately.
To achieve such a scheme a routing and switching logic is required to select between various external devices or their simulators based on their availability. To develop such an interface we make use of Complex Programmable Logic Device (CPLD) which will be programmed as per the logic required.
Fig. 1 Basic Block Diagram
The routing in the CPLD is done by using the 8-bit control lines called general purpose input output lines (gpio lines). The gpio lines will be decoded by the decoder in the CPLD to obtain the source and the destination address. Using these addresses the routing will be done by the CPLD.
In case of the module failure, an alternative will be provided to switch to the default condition (manual operation). So that the execution does not get delayed or halted.
II. PROJECT OVERVIEW
A. IMPLEMENTATION
Considering there are 6 serial channels on the output side on which the 6 processes are operated, then there will be 6 real devices and their 6 corresponding simulators on the input side to serve the requesting processes. There are 6 serial channels on the input side, on which the 6 simulators of the external devices will be opened. Any simulator can be opened on any of the 6 serial channels. These serial channels are connected to the transceiver block. Also there are 6 external devices connected/opened on another 6 serial channels which are connected to another transceiver as shown. The output of this transceiver is given to the switching block.
Another i/p to the routing block is the gpio lines used as the control lines. Out of 8-bit data in the gpio lines, 6-bits will be decoded to obtain the source and the destination address. Source address specifies the channel on which the real/simulated data is present or opened. Destination address specifies the address of the channel on which a request for the device was made by a process.
One bit is used as the valid bit which tells whether the data is present on any channels and if the routing is required. Other bit of the gpio lines will be used to select between the real device or its simulator. Hence the final output of the CPLD will be either the requested real device or its simulator.
As shown in the fig.1 the routing and the switching block together is the CPLD. The output thus obtained from the CPLD is again fed to another transceiver, which will be then given to a bypass switch.
A bypass is provided to switch to the default state in case of the module failure, so that the execution does not get delayed or halted. The bypass is essentially a relay. If there is no input coming from the module to the relay, the relay senses it and switches to the default state.
The 6 external devices are connected by default to their corresponding output channels on which the processes are opened. So that in case of the module failure, the awaiting process will gain access to the requested real devices with or without any delay depending on its availability.
B. BACKGROUND
Hardware components:
1. XC2C256-7TQ144I CPLD
A Complex Programmable Logic Device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.
The Cool Runner™-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved.
• Optimized for 1.8V systems
• Industry’s fastest low power CPLD
• Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD
• Multi-voltage I/O operation — 1.5V to 3.3V
2. MAX3491ESD Transceiver
We use the RS-422 transceiver IC from Maxim Integrated Products which is MAX 3491.This IC will convert double ended signal which is coming from the cabinets or from the systems into single ended, and thus reducing the number of pin connections to CPLD. MAX 3491 are 3.3V, low-power transceivers for RS-422 communication. Each part contains one driver and one receiver. This IC will transmit up to 10Mbps.
3. BUFFER-SN74LVC16T245
This 16-bit non inverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated.