ACE RT MEMORY MANAGEMENT OPTIONS

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INTRODUCTION
The ACE RT architecture offers a high degree of programmable
flexibility. As a result, it is able to provide a
solution to a wide variety of applications. One of the
salient attributes, which is the main subject of this application
note, is the ACE's memory management architecture.
This includes a variety of options, most of which
are programmable on a subaddress basis.


MEMORY MAP, DATA STRUCTURES
Table 1 illustrates a typical memory map for the ACE
RT with the enhanced mode features enabled. The
two Stack Pointers reside in fixed locations in the
shared RAM address space: address 0100 (hex) for
the Area A Stack Pointer and address 0104 for the
Area B Stack Pointer. In addition to the Stack Pointer,
for the ACE enhanced RT, there are several other
areas of the ACE address space that are designated
as fixed locations. These are for the Area A and Area
B Lookup Tables, the Mode Code Selective Interrupt
Table, the Mode Code Data Table, the Busy Lookup
Table, and the Command Illegalizing Table.

ACE RT MEMORY MANAGEMENT OPTIONS

Words as well as the individual data block pointers.
The actual Stack RAM area as well as the individual
data blocks may be located in any of the non-fixed
areas in the shared RAM address space.
Table 2 illustrates the organization of the RT Lookup
Tables. It should be noted that if SEPARATE BROADCAST
DATA, bit 2 of Configuration Register #2, is logic
"0", the data block pointers for both broadcast and
nonbroadcast receive messages will be stored in the
first 32 locations of the lookup tables. If SEPARATE
BROADCAST DATA is logic "l", the pointers to data
words for broadcast messages are stored in the third
block of 32 locations within the respective lookup table.



SUBADDRESS MEMORY MANAGEMENT
The most salient attribute of the ACE's RT architecture
is the flexibility offered by its options for subaddress
memory management. The ACE supplies a
host of programmable features to support ease of
operation, guarantee data consistency, and facilitate
bulk data transfers.
The ability to program the memory management
mechanism on a subaddress basis is essential to
most complex system designs since the data content
that will be transferred to and from an RT generally
varies in size (bulk data versus single messages).


SUBADDRESS CONTROL WORD
If ENHANCED RT MEMORY management has
been enabled by means of bit I of Configuration
Register #2, each of the 32 Subaddress Control
Words specifies the memory management and
interrupt schemes for the respective subaddress.
Refer to Tables 4 and 5.