PROCESSOR-TO-ACE INTERFACES

[attachment=18016]

INTRODUCTION
Among the salient features of DDC's Advanced
Communication Engine (ACE) terminals is the flexibility
of their processor and memory interface. In
today's applications, there are designs entailing the
use of multiple processors and/or multiple 1553
interfaces. Some types of systems employ both
multiple processors and multiple 1553 interfaces.
The two most common forms of the interface are
direct memory access (DMA) and shared RAM.
There are variations on each of these,


SHARED RAM CONFIGURATION
Figures 3 and 4 illustrate shared RAM interfaces
between 16-bit and 8bit processors, respectively,
and an ACE terminal. In a shared RAM interface, tristate
buffers are provided between the processor
address and data buses and the buses connecting
to the 1553 buffer memory and terminal logic. In this
configuration, the processor always has access to
its own buses. That is, the ACE will never request the
use of the CPU buses. This provides the advantage
of allowing the ACE to access the buffer RAM while
the CPU is able to simultaneously use its buses to
access its memory or I/O. In this way, a shared RAM
interface utilizes less of the CPU's bandwidth than
does a DMA interface.


8-BIT MODE
In the 8-bit buffered mode (Figure 4), the input 16/8-BIT
must be strapped to logic "0" and the CPU's data bus
must be connected to D15-D8 and D7-D0. The LSB of
the processor address bus (processor A0) must be connected
to the input MSB/LSB for upper/lower byte selection.
In order to accommodate the different "A0" and
"byte ordering" conventions of various 8-bit processor
families, the inputs POLARITY_SEL and TRIGGER_
SEL need to be strapped to logic "0" or " I ".
See Figure 4 and Table 1.


BOARD SPACE, RAM SIZE
An integrated 1553 terminal, such as the ACE, has
an inherent advantage over a "discrete" 1553
mechanization in implementing a shared RAM
interface. That is, it is able to minimize PC board
space requirements by incorporating all of the elements
within a single package: transceiver, protocol,
RAM, and buffers. The BU-65170RT, BU-61580
BC/RT/MT, and BU-61590 (Universal) ACE terminals
include 4K words of internal RAM. The BU-
61585 BC/RT/MT ACE contains an additional 8K X
17 of internal RAM. The BU-61585 supports two different
organizations for its internal memory: (1) 8K
X 17, with parity generation and checking on all
RAM accesses; and (2) 12K X 16 without the RAM
parity functions.