POWER OPTIMIZATION OF LINEAR FEEDBACK
shift REGISTER(LFSR)FOR LOW POWER BIST


  POWER OPTIMIZATION OF LINEAR FEEDBACK.ppt (Size: 1.11 MB / Downloads: 7)

ABSTRACT

This project proposes a low power LFSR for TPG technique with reducing power dissipation during testing .
The correlations between the consecutive patterns are higher during normal mode than during testing
The proposed approach uses the concept of reduce the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the Correlation between the successive bits.

DESIGN FOR TESTABILITY:

For complex circuits, hierarchical approach is used. The advantage of hierarchical approach is that every block is tested separately. Test input is given to each block and output is observed and verified.
DFT (design for testability) is the action of placing features in a chip design process to enhance the ability to generate vectors, achieve a measured quality level or reduce cost of testing. The conventional DFT approaches use scan and BIST.
In this paper a modified low power LFSR are used in which the number of transitions of test pattern are reduced testing.

BUILT IN SELF TEST:

BIST is the design technique in which parts of a circuits are used to test the circuit itself.
BIST is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient, and less costly.
The concept of BIST is applicable to just about any kind of circuit, so its implementation can vary widely as the product diversity that it caters to.

CONCLUSION

After incorporating the so designed algorithm in the LFSR of BIST, it will be verified that the power of the LFSR is reduced.
By using low power LFSR technique, we can observe that the power in BIST implementation can be further decreased.