[attachment=3267]
Multisensor Strategies to Assist Blind People A Clear-Path Indicator
ABSTRACT
It is a difficult task for the blind people to walk around the road side without any bodyâ„¢s help. This projects demonstrate the Clear path indicator for the blind people which gives them feel comfortable to walk around the road by without anybodyâ„¢s help, by using an embedded device with multiple sensor, which gives an indication to the blind people whenever there is obstacle comes on their way to the walking and this indication will be given with the help of Buzzer sound which gives the audible indication to the blind people.
The stick of the blind people is equipped with multiple sensors and and microcontroller device and gives the buzzer whenever there is an obstacle.
In this project we are going to use LPC2148 (ARM7) based microcontroller, which the current dominant microcontroller in mobile based products and software development Tool as Keil, flash magic for loading hex file in to the microcontroller
SOFTWARE: Embedded ËœCâ„¢
TOOLS: Keil, Flashmagic.
TARGET DEVICE: LPC2148(ARM7) microcontroller.
APPLICATIONS: Clear path indication to the blind people
ADVANTAGES: Low cost and easily solution no need for helper for the blind people. As they can go safely with help of this device
REFERENCE: The 8051 micro controller and embedded systems by Mazidi and LPC datasheets, and the user manual for the LPC2148.
ARM System Developerâ„¢s Guide
-Andrew N.SLOSS
-Domenic Symes
-Chris Wright
INDEX
1. Introduction to Embedded Systems
2. ARM and Its Architecture
3. LPC2148 Microcontrollers
4. IR Modules & LDR
5. Working flow of the project Block diagram and Schematic diagram
6. Source code
7. Keil software
8. Conclusion
9. Bibiliography
CHAPTER 1
INTRODUCTION TO EMBEDDED SYSTEM
INTRODUCTION TO EMBEDDED SYSTEM
EMBEDDED SYSTEM
An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, sometimes with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming. Embedded systems have become very important today as they control many of the common devices we use.
Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale.
Physically, embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, or the systems controlling nuclear power plants. Complexity varies from low, with a single microcontroller chip, to very high with multiple units, peripherals and networks mounted inside a large chassis or enclosure.
In general, "embedded system" is not an exactly defined term, as many systems have some element of programmability. For example, Handheld computers share some elements with embedded systems †such as the operating systems and microprocessors which power them †but are not truly embedded systems, because they allow different applications to be loaded and peripherals to be connected.
An embedded system is some combination of computer hardware and software, either fixed in capability or programmable, that is specifically designed for a particular kind of application device. Industrial machines, automobiles, medical equipment, cameras, household appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone and PDA) are among the myriad possible hosts of an embedded system. Embedded systems that are programmable are provided with a programming interface, and embedded systems programming is a specialized occupation.
Certain operating systems or language platforms are tailored for the embedded market, such as Embedded Java and Windows XP Embedded. However, some low-end consumer products use very inexpensive microprocessors and limited storage, with the application and operating system both part of a single program. The program is written permanently into the system's memory in this case, rather than being loaded into RAM (random access memory), as programs on a personal computer are.
APPLICATIONS OF EMBEDDED SYSTEM
We are living in the Embedded World. You are surrounded with many embedded products and your daily life largely depends on the proper functioning of these gadgets. Television, Radio, CD player of your living room, Washing Machine or Microwave Oven in your kitchen, Card readers, Access Controllers, Palm devices of your work space enable you to do many of your tasks very effectively. Apart from all these, many controllers embedded in your car take care of car operations between the bumpers and most of the times you tend to ignore all these controllers.
In recent days, you are showered with variety of information about these embedded controllers in many places. All kinds of magazines and journals regularly dish out details about latest technologies, new devices; fast applications which make you believe that your basic survival is controlled by these embedded products. Now you can agree to the fact that these embedded products have successfully invaded into our world. You must be wondering about these embedded controllers or systems. What is this Embedded System
The computer you use to compose your mails, or create a document or analyze the database is known as the standard desktop computer. These desktop computers are manufactured to serve many purposes and applications.
You need to install the relevant software to get the required processing facility. So, these desktop computers can do many things. In contrast, embedded controllers carryout a specific work for which they are designed. Most of the time, engineers design these embedded controllers with a specific goal in mind. So these controllers cannot be used in any other place.
Theoretically, an embedded controller is a combination of a piece of microprocessor based hardware and the suitable software to undertake a specific task.
These days designers have many choices in microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available variety really may overwhelm even an experienced designer. Selecting a right microprocessor may turn out as a most difficult first step and it is getting complicated as new devices continue to pop-up very often.
In the 8 bit segment, the most popular and used architecture is Intel's 8031. Market acceptance of this particular family has driven many semiconductor manufacturers to develop something new based on this particular architecture. Even after 25 years of existence, semiconductor manufacturers still come out with some kind of device using this 8031 core.
Military and aerospace software applications
From in-orbit embedded systems to jumbo jets to vital battlefield networks, designers of mission-critical aerospace and defense systems requiring real-time performance, scalability, and high-availability facilities consistently turn to the LynxOS® RTOS and the LynxOS-178 RTOS for software certification to DO-178B.
Rich in system resources and networking services, LynxOS provides an off-the-shelf software platform with hard real-time response backed by powerful distributed computing (CORBA), high reliability, software certification, and long-term support options.
The LynxOS-178 RTOS for software certification, based on the RTCA DO-178B standard, assists developers in gaining certification for their mission- and safety-critical systems. Real-time systems programmers get a boost with LynuxWorks' DO-178B RTOS training courses.
LynxOS-178 is the first DO-178B and EUROCAE/ED-12B certifiable, POSIX®-compatible RTOS solution.
Communications applications
"Five-nines" availability, CompactPCI hot swap support, and hard real-time responseâ€LynxOS delivers on these key requirements and more for today's carrier-class systems. Scalable kernel configurations, distributed computing capabilities, integrated communications stacks, and fault-management facilities make LynxOS the ideal choice for companies looking for a single operating system for all embedded telecommunications applicationsâ€from complex central controllers to simple line/trunk cards.
LynuxWorks Jumpstart for Communications package enables OEMs to rapidly develop mission-critical communications equipment, with pre-integrated, state-of-the-art, data networking and porting software componentsâ€including source code for easy customization.
The Lynx Certifiable Stack (LCS) is a secure TCP/IP protocol stack designed especially for applications where standards certification is required.
Electronics applications and consumer devices
As the number of powerful embedded processors in consumer devices continues to rise, the BlueCat® Linux® operating system provides a highly reliable and royalty-free option for systems designers.
And as the wireless appliance revolution rolls on, web-enabled navigation systems, radios, personal communication devices, phones and PDAs all benefit from the cost-effective dependability, proven stability and full product life-cycle support opportunities associated with BlueCat embedded Linux. BlueCat has teamed up with industry leaders to make it easier to build Linux mobile phones with Java integration.
For makers of low-cost consumer electronic devices who wish to integrate the LynxOS real-time operating system into their products, we offer special MSRP-based pricing to reduce royalty fees to a negligible portion of the device's MSRP.
Industrial automation and process control software
Designers of industrial and process control systems know from experience that LynuxWorks operating systems provide the security and reliability that their industrial applications require.
From ISO 9001 certification to fault-tolerance, POSIX conformance, secure partitioning and high availability, we've got it all. Take advantage of our 20 years of experience.
MICROCONTROLLER VERSUS MICROPROCESSOR
What is the difference between a Microprocessor and Microcontroller By microprocessor is meant the general purpose Microprocessors such as Intel's X86 family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's 680X0 family (68000, 68010, 68020, 68030, 68040, etc). These microprocessors contain no RAM, no ROM, and no I/O ports on the chip itself. For this reason, they are commonly referred to as general-purpose Microprocessors.
A system designer using a general-purpose microprocessor such as the Pentium or the 68040 must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more expensive, they have the advantage of versatility such that the designer can decide on the amount of RAM, ROM and I/O ports needed to fit the task at hand. This is not the case with Microcontrollers.
A Microcontroller has a CPU (a microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, the RAM, ROM, I/O ports and the timer are all embedded together on one chip; therefore, the designer cannot add any external memory, I/O ports, or timer to it. The fixed amount of on-chip ROM, RAM, and number of I/O ports in Microcontrollers makes them ideal for many applications in which cost and space are critical.
In many applications, for example a TV remote control, there is no need for the computing power of a 486 or even an 8086 microprocessor. These applications most often require some I/O operations to read signals and turn on and off certain bits.
MICROCONTROLLERS FOR EMBEDDED SYSTEMS
In the Literature discussing microprocessors, we often see the term Embedded System. Microprocessors and Microcontrollers are widely used in embedded system products. An embedded system product uses a microprocessor (or Microcontroller) to do one task only. A printer is an example of embedded system since the processor inside it performs one task only; namely getting the data and printing it. Contrast this with a Pentium based PC. A PC can be used for any number of applications such as word processor, print-server, bank teller terminal, Video game, network server, or Internet terminal. Software for a variety of applications can be loaded and run. Of course the reason a pc can perform myriad tasks is that it has RAM memory and an operating system that loads the application software into RAM memory and lets the CPU run it.
In an Embedded system, there is only one application software that is typically burned into ROM. An x86 PC contains or is connected to various embedded products such as keyboard, printer, modem, disk controller, sound card, CD-ROM drives, mouse, and so on. Each one of these peripherals has a Microcontroller inside it that performs only one task. For example, inside every mouse there is a Microcontroller to perform the task of finding the mouse position and sending it to the PC. Table 1-1 lists some embedded products.
CHAPTER 2
ARM Architecture & Programming
ARM Architecture & Programming
ARM History
Architecture
ARM register file & modes of operation
Instruction Set
ARM History
The ARM (Acorn RISC Machine)architecture is developed at Acron Computer Limited of Cambridge, England between 1983-1985. ARM Limited founded in 1990. ARM became as the Advanced RISC Machine is a 32-bit RISC processor architecture that is widely used in embedded designs. ARM cores licensed to semiconductor partners who fabricate and sell to their customers. ARM does not fabricate silicon itself
Because of their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal. As of 2007, about 98 percent of the more than a billion mobile phones sold each year use at least one ARM CPU.
Today, the ARM family accounts for approximately 75% of all embedded 32-bit RISC CPUs, making it the most widely used 32-bit architecture. ARM CPUs are found in most corners of consumer electronics, from portable devices (PDAs, mobile phones, iPods and other digital media and music players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers).
ARM does not manufacture the CPU itself, but licenses it to other manufacturers to integrate them into their own system
ARM architecture
RISC:
RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.
History :
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar philosophy which has become known as RISC. Certain design features have been characteristic of most RISC processors:
¢ one cycle execution time : RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU and a technique called ;
¢ pipelining : a techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions;
¢ large number of registers : the RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory
CISC RISC
Price/Performance Strategies
Price: move complexity from software to hardware.
Performance: make tradeoffs in favor of decreased code size, at the expense of a higher CPI. Price: move complexity from hardware to software
Performance: make tradeoffs in favor of a lower CPI, at the expense of increased code size.
Design Decisions
¢ Execution of instructions takes many cycles
¢ Design rules are simple thus core operates at higher clock frequencies
¢ Memory-to-memory addressing modes.
¢ A microcode control unit.
¢ Spend fewer transistors on registers. ¢ Simple, single-cycle instructions that perform only basic functions. Assembler instructions correspond to microcode instructions on a CISC machine.
¢ Design rules are more complex and operates at lower clock frequencies
¢ Simple addressing modes that allow only LOAD and STORE to access memory. All operations are register-to-register.
¢ direct execution control unit.
¢ spend more transistors on multiple banks of registers.
¢ use pipelined execution to lower CPI.
Based upon RISC Architecture with enhancements to meet requirements of embedded applications ARM is having
1. A large uniform register file
2. Load-store architecture ,where data processing operations operate on register contents only
3. Uniform and fixed length instructions
4. 32 -bit processor
5. Instructions are 32-bit long
6. Good Speed/Power Consumption Ratio
7. High Code Density
Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both busses . Greater amount of instruction parallelism is possible in this architecture. Most DSPs use Harvard architecture for streaming data. The only difference in Harvard architecture to that of Von Neumann architecture is that the program and data memories are separated and use physically separate transmission paths . Enables the machine to transfer instructions and data simultaneously enhances performance. Harvard architecture is more commonly used in specialized microprocessors for real-time and embedded application. However, only the early DSP chips use the Harvard architecture because of the cost. The greatest disadvantage of the Harvard architecture is which needs twice as many address and data pins on the chips
A Von Neumann architecture store program and data in the same memory area with a single bus. So this bus only is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time. Most of the general-purpose microprocessors such as Motorola 68000 and Intel 80x86 use this architecture. It is simple in hardware implementation, but the data and program are required to share a single bus.
ARM Processor Core :
The figure shows the ARM core dataflow model. In which the ARM core as functional units connected by data buses,. And the arrows represent the flow of data, the lines represent the buses, and boxes represent either an operation unit or a storage area. The figure shows not only the flow of data but also the abstract components that make up an ARM core.
Fig : ARM core dataflow model
In the above figure the Data enters the processor core through the Data bus. The data may be an instruction to execute or a data item. This ARM core represents the Von Neumann implementation of the ARM data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two different buses.
The instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular instruction set.
The ARM processor ,like all RISC processors, use a load-store architecture. This means it has two instruction types for transferring data in and out of the processor : load instructions copy data from memory to registers in the core, and conversely the store instructions copy data from registers to memory. There are no data processing instructions that directly manipulate data in memory. Thus, data processing is carried out solely in registers.
Data items are placed in the register file “ a storage bank made up of 32-bit registers. Since the ARM core is a 32- bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values.
The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a register.
The ALU ( arithmetic logic unit ) or MAC ( multiply “ accumulate unit ) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and store instructions use the ALU to generate an address to be held in the address register and broadcast on the Address bus.
One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide range of expressions and addresses.
After passing through the functional units, the result in Rd is written back to the register file using the Result bus. For load and store instructions the incrementer updates the address register before the core reads or writes the next register value from or to the next sequential memory location. The processor continues executing instructions until an exception or interrupt changes the normal execution flow.
*ARM Bus Technology :
Embedded systems use different bus technologies. Most common PC bus technology is the Peripheral Component Interconnect ( PCI ) bus. Which connects devices such as video card and disk controllers to the X86 processor bus. This type of technology is called External or Off chip bus technology.
Embedded devices use an on-chip bus that is internal to the chip and allows different peripheral devices to be inter connected with an ARM core.
There are two different types of devices connected to the bus
1. Bus Master
2. Bus Slave
1. Bus Master : A logical device capable of initiating a data transfer with another device across the same bus (ARM processor core is a bus Master ).
2. Bus Slave : A logical device capable only of responding to a transfer request from a bus master device ( Peripherals are bus slaves )
Generally A Bus has two architecture levels
Physical lever : Which covers electrical characteristics an bus width (16,32,64 bus).
Protocol level : which deals with protocol
NOTE :- ARM is primarily a design company . It seldom implements the electrical characteristics of the bus , but it routinely specifies the bus protocol
AMBA (Advanced Microcontroller Bus Architecture )Bus protocol :
AMBA Bus was introduced in 1996 and has been widely adopted as the On Chip bus architecture used for ARM processors.
The first AMBA buses were
1. ARM System Bus ( ASB )
2. ARM Peripheral Bus ( APB )
Later ARM introduced another bus design called the ARM High performance Bus ( AHB )
Using AMBA
i. Peripheral designers can reuse the same design on multiple projects
ii. A Peripheral can simply be bolted on the On Chip bus with out having to redesign an interface for each different processor architecture.
This plug-and-play interface for hardware developers improves availability and time to market.
AHB provides higher data throughput than ASB because it is based on centralized multiplexed bus scheme rather than the ASB bidirectional bus design. This change allows the AHB bus to run at widths of 64 bits and 128 bits
ARM introduced two variations on the AHB bus
1. Multi-layer AHB
2. AHB-Lite
In contrast to the original AHB , which allows a single bus master to be active on the bus at any time , the Multi-layer AHB bus allows multiple active bus masters.
AHB-Lite is a subset of the AHB bus and it is limited to a single bus master. This bus was developed for designs that do not require the full features of the standard AHB bus.
AHB and Multiple-layer AHB support the same protocol for master and slave but have different interconnects. The new interconnects in Multi-layer AHB are good for systems with multiple processors. They permit operations to occur in parallel and allow for higher throughput rates.
ARCHITECTURE Revisions :
Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation
The ISA has evolved to keep up with the demands of the embedded market. This evolution has been carefully managed by ARM , so that code written to execute on an earlier architecture revision will also execute on a later revision of the architecture.
The nomenclature identifies individual processors and provides basic information about the feature set.
NOMENCLATURE :
ARM uses the nomenclature shown below is to describe the processor implementations.The letters and numbers after the word ARM indicate the features a processor may have.
ARM { x }{ y }{ z }{ T }{ D }{ M }{ I }{ E }{J }{ F }{ -S }
x family
y memory management / protection unit
z cache
T Thumb 16 bit decoder
D JTAG debug
M fast multiplier
I EmbeddedICE macrocell
E enhanced instruction ( assumes TDMI )
J Jazelle
F vector floating-point unit
S synthesizible version
All ARM cores after the ARM7TDMI include the TDMI features even though they may not include those letters after the ARM label
The processor family is a group of processor implementations that share the same hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all share the same family characteristics and belong to the ARM7 family
JTAG is described by IEEE 1149.1 standard Test Access Port and boundary scan architecture. It is a serial protocol used by ARM to send and receive debug information between the processor core and test equipment
EmbeddedICE macrocell is the debug hardware built into the processor that allows breakpoints and watchpoints to be set
Synthesizable means that the processor core is supplied as source code that can be compiled into a form easily used by EDA tools
Introduction to ARM7TDMI core
The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macrocell optimized to provide the best combination of performance, power and area characteristics. The ARM7TDMI core enables system designers to build embedded devices requiring small size, low power and high performance.
ARM7TDMI Features
¢ 32/16-bit RISC architecture (ARM v4T)
¢ 32-bit ARM instruction set for maximum performance and flexibility
¢ 16-bit Thumb instruction set for increased code density
¢ Unified bus interface, 32-bit data bus carries both instructions and data
¢ Three-stage pipeline
¢ 32-bit ALU
¢ Very small die size and low power consumption
¢ Fully static operation
¢ Coprocessor interface
¢ Extensive debug facilities (EmbeddedICE debug unit accessible via JTAG interface unit)
Benefits
¢ Generic layout can be ported to specific process technologies
¢ Unified memory bus simplifies SoC integration process
¢ ARM and Thumb instructions sets can be mixed with minimal overhead to support application requirements for speed and code density
¢ Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7 Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's quite easy to port your design to higher level microcontroller or microprocessor
¢ Static design and lower power consumption are essential for battery -powered devices
¢ Instruction set can be extended for specific requirements using coprocessors
¢ EmbeddedICE-RT and optional ETM units enable extensive, real-time debug facilities
ARM7TDMI Microcontrollers
1. Available ARM7TDMI Microcontrollers
2. Analog Devices ADuC 7xxx
3. Atmel AT91SAM7
4. Freescale MAC7100
5. NXP/Philips LPC2000
6. ST STR710
7.Texas Instruments TMS470
2.3 ARM Register file & modes of operation
Registers : General Purpose registers hold either data or address they are identified with the letter r prefixed to the register number. All registers are of 32 bits.
ARM has 37 registers in total, all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access a particular set of r0-r12 registers, a particular r13 (the stack pointer) and r14 (link register), r15 (the program counter), cpsr (the current program status register)
and privileged modes can also access a particular spsr (saved program status register).
In user mode 16 data registers and 2 status registers are visible. Depending upon context, register r13 and r14 can also be used as General Purpose Registers. In ARM state the registers r0 to r13 are Orthogonal that means - any instruction which use r0 can as well be used with any other General Purpose Register (r1-r13).
The ARM processor has three registers assigned to a particular task or special function: r13,r14 and r15. They are frequently given different labels to differentiate them from the other registers.
Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack in the current processor mode
Register r14 is called the page link register ( lr ) and is where the core puts the return address whenever it calls a subroutine.
Register r15 is the program counter ( pc ) and contains the address of the next instruction to be fetched by the processor
The register file contains all the registers available to a programmer. Which registers are visible to the programmer depend upon the current mode of the processor.
Current program status register :
The ARM core uses the cpsr to monitor and control internal operations. The cpsr is a dedicated 32-bit register and resides in the register file. The following figure shows the generic program status register.
Fig: Program Status Register
The control bit field contains the processor mode, state , and interrupt mask bits (I,F). Reserved bits are allocated for the future versions purpose.
The N, Z, C and V are condition code flags will be changed as a result of arithmetic and logical operations in the processor
N : Negative. Z : Zero. C : Carry. V : Overflow
The I and F bits are the interrupt disable bits
The M0, M1, M2, M3 and M4 bits are the mode bits
Processor Modes: Processor modes determine which register are active, and access rights to CPSR register itself. Each processor mode is either Privileged or Non-privileged. ARM has seven modes. These 7 modes are divided into two types.
Privileged :- Full read-write access to the CPSR. Under this we are having Abort, Fast interrupt request, Interrupt request, Supervisor,System and Undefined
Abort (10111) :
when there is a failed attempt to access memory
Fast interrupt Request (FIQ(10001)) & interrupt request(10010) :
correspond to interrupt levels available on ARM
Supervisor mode(10011) :
state after reset and generally the mode in which OS kernel executes
System mode(11111) :
special version of user mode that allows full read-write access of CPSR
Undefined(11011) :
when processor encounters an undefined instruction
Non-privileged :- Only read access to the control filed of CPSR but read-write access to the condition flags.
User(10000): User mode is user for programs and applications. And this the normal mode
Banked Registers :
Register file contains in all 37 registers. 20 registers are hidden from program at different times. These registers are called banked registers. Banked registers are available only when the processor is in a particular mode. Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 register
SPSR:
Each privileged mode (except system mode) has associated with it a Save Program Status Register, or SPSR. This SPSR is used to save the state of CPSR (Current program status Register) when the privileged mode is entered in order that the user state can be fully restored when the user processor is resumed
Mode Changing :
Mode changes by writing directly to CPSR or by hardware when the processor responds to exception or interrupt
To return to user mode a special return instruction is used that instructs the core to restore the original CPSR and banked registers
ARM Instruction Set
In this chapter we are going to discuss about the most commonly used Instruction Set of ARM. Different ARM architectures revisions support different instructions. However new revisions usually add instructions and remain backwardly compatible. The following shows the type of instructions that ARM support.
I. Data Processing Instructions
II. Branch Instructions
III. Load-store Instructions
IV. Software Interrupt Instruction
V. Program Status Register Instructions
I. Data Processing Instructions :-
The data processing instructions manipulate data within registers. Most data processing instructions can process one of their operands using the barrel shifter. If we use the S suffix on a data processing instruction, then it updates the flags in the cpsr. Move and logical operations update the carry flag C, negative flag N, and Zero flag Z. The carry flag is set from the result of the barrel shift as the last bit shifted out. The N flag is set to bit 31 of the result. The Z flag is set if the result is zero. The following instructions are Data processing instructions.
i). Move instructions: This instruction is used to move the content of one register to another register. The below instructions are the Move instructions
MOV : move a 32-bit value into a register Rd=RS
MOVN : move the NOT of the 32 bit value into a register Rd= ~RS
ii). Barrel Shifter :- A unique and powerful feature of ARM processor is ability to shift the 32-bit binary pattern in one of the source registers left or right by a specific number of positions before it enters the ALU. This is done by using the Barrel shifter. This preprocessing or shift occurs within the cycle time of the instruction. The five different shift operations that we can use within the barrel shifter given below.
LSL : logical shift left
LSR : logical shift right
ASR : arithmetic right shift
ROR : rotate right
RRX : rotate right extended
iii. Arithmetic Instructions : The arithmetic instructions implement and subtraction of 32-bit signed and unsigned values. Some of the instructions of Arithmetic instructions are given below.
ADD :add two 32-bit values.
ADC :add two 32-bit values and carry
SUB
ubtract two 32-bit values
SBC : subtract with carry of two 32-bit values
RSB : reverse subtract of two 32-bit values
RSC : reverse subtract with carry of two 32-bit values
iv. Logical Instructions : Performs the logical operations on two source registers
AND : logical bitwise AND of two 32-bit values
ORR : logical bitwise OR of two 32-bit values
EOR : logical exclusive OR of two 32-bit vlaues.
BIC : Logical bit clear (AND NOT)
v. Comparison Instructions : The comparison instructions are used to compare or test a register with a 32 bit value. They update the cpsr flag bits (N, Z, C, V) according to the result, but do not affect other registers. After the bits have been set, the information can then be used to change program flow by using conditional execution. We do not need to apply the S suffix for comparison instructions to update the flag. The following instructions are belong Comparison instructions
CMP (compare) : flags set as a result of R1-R2
CMN (compare negated) : flags set as a result of R1+R2
TST (test for equality of two 32-bit values) : flags set as a result of R1&R2
TEQ (test for equality of two 32-bit values) : flags set as a result of R1^R2
vi. Multiply Instructions : The multiply instructions multiply the content of a pair of registers and , depending upon the instruction, accumulate the results in with another register. The long multiplies accumulate onto a pair of registers representing a 64 bit value. The final result is placed in a destination register or a pair of registers.
MUL : multiply
MLA : multiply and accumulate
Long Multiply Instructions : (Produce 64 bit values,result will be placed in two 32 bit values)
SMLAL : signed multiply accumulate long
SMULL : signed multiply accumulate
UMLAL : unsigned multiply accumulate long
UMULL : unsigned multiply long
II. Branch Instructions :- A branch instruction changes the flow of execution or is used to call a routine. This type of instruction allows programs to have subroutines, if-then-else structures, and loops. The change of execution flow forces the program counter pc to point to new address. The below shown instructions are Branch instructions.
B : branch
BL : branch with link
BX : branch exchange
BLX : branch exchange with link
III. Load-store Instructions :- Load-store instructions transfer data between memory and processor registers.
There are three types of load-store instructions :
i. single register transferring
ii. Multiple register transfer
iii. Swap
Single register transferring :- These instructions are used for moving a single data item in and out of a register. The data types supported are signed and unsigned words(32-bit), halfwords(16-bit), and bytes. The following instructions are various load-store single-register transfer instructions.
LDR : load word into a register
STR : save byte or word from a register
LDRB : load byte into a register
STRB : save byte from a register
LDRH : load halfword into a register
STRH : save halfword into a register
LDRSB : load signed byte into a register
LDRSH : load signed halfword into a register
Multiple register transfer : - Load-store multiple instructions can transfer multiple registers between memory and the processor in a single instruction. The transfer occurs from a base address register Rn pointing into memory. Multiple-register transfer instructions are more efficient from single-register transfers for moving blocks of data around memory and saving and restoring context and stacks. If an interrupt has been raised, then it has no effect until the load-store multiple instruction is complete.
LDM : load multiple registers
STM : save multiple registers
Swap :- The swap instruction is a special case of a load-store instruction. It swaps the contents of memory with the contents of a register. This instruction is an atomic operation- it reads and writes a location in the same bus operation, preventing any other instruction from reading or writing to that location until it completes.
IV. Software Interrupt Instruction :- A software interrupt instruction ( SWI ) causes a software interrupt exception, which provides a mechanism for applications to call operating system routines. The following instruction comes under software interrupt instruction.
SWI : software interrupt
V. Program Status Register Instructions :- The ARM instruction set provides two instructions to directly control a program status ( psr ).
MRS : This instruction transfers the contents of either the cpsr or spsr into a register
MSR : This instruction transfers the content of a register into the cpsr or spsr
Together the above two instructions are used to read and write the cpsr or spsr
CHAPTER 3
LPC2148 MICROCONTROLLER
LPC 2148 MICROCONTROLLER
General description of LPC 2148:
The LPC2148 microcontrollers is based on a 32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine microcontrollers with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb
mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADCs, 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems.
General overview of in system programming (ISP):
In-System Programming (ISP) is a process whereby a blank device mounted to a circuit board can be programmed with the end-user code without the need to remove the device from the circuit board. Also, a previously programmed device can be erased and Re programmed without removal from the circuit board. In order to perform ISP operations the microcontroller is powered up in a special ISP mode. ISP mode allows the microcontroller to communicate with an external host device through the serial port, such as a PC or terminal. The microcontroller receives commands and data from the host, erases and reprograms code memory, etc. Once the ISP operations have been completed the device is reconfigured so that it will operate normally the next time it is either reset or power removed and reapplied. All of the Philips microcontrollers shown in Table 1 and Table 2 have a 1 kbyte factory-masked ROM located in the upper 1 kbyte of code memory space from FC00 to FFFF. This 1 kbyte ROM is in addition to the memory blocks shown in Table 1 and Table 2. This ROM is referred to as the Bootrom. This Bootrom contains a set of instructions which allows the microcontroller to perform a number of Flash programming and erasing functions. The Bootrom also provides communications through the serial port. The use of the Bootrom is key to the concepts of both ISP and In-Application Programming (IAP). The contents of the bootrom are provided by Philips and masked into every device. When the device is reset or power applied, and the EA/ pin is high or at the VPP voltage, the microcontroller will start executing instructions from either the user code memory space at address 0000h (normal mode) or will execute instructions from the Bootrom (ISP mode).
General Overview of IN APPLICATION PROGRAMMING:
Some applications may have a need to be able to erase and program code memory under the control fo the application. For example, an application may have a need to store calibration information or perhaps need to be able to download new code portions. This ability to erase and program code memory in the end-user application is In-Application Programming (IAP). The Bootrom routines which perform functions on the Flash memory during ISP mode such as programming, erasing, and reading, are also available to end-user programs. Thus it is possible for an end-user application to perform operations on the Flash memory. A common entry point (FFF0h) to these routines has been provided to simplify interfacing to the end-users application. Functions are performed by setting up specific registers as required by a specific operation and performing a call to the common entry point. Like any other subroutine call, after completion of the function, control will return to the end-userâ„¢s code. The Bootrom is shadowed with the user code memory in the address range from FC00h to FFFFh. This shadowing is controlled by the ENBOOT bit (AUXR1.5). When set, accesses to internal code memory in this address range will be from the boot ROM. When cleared, accesses will be from the userâ„¢s code memory. It will be NECESSARY for the end-userâ„¢s code to set the ENBOOT bit prior to calling the common entry point for IAP operations, even for devices with 16 kbyte, 32 kbyte, and 64 kbyte of internal code memory. (ISP operation is selected by certain hardware conditions and control of the ENBOOT bit is automatic when ISP mode is activated).
FEATURES OF LPC2148(ARM7) ARCHITECTURE
Key features:
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package
8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory; 128-bit wide interface/accelerator enables high-speed 60 MHz operation
In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software, single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms.
Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high-speed tracing of instruction execution
USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM
In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA
One or two (LPC2141/42 vs, LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 ms per channel Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only)
Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities
Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package
Up to 21 external interrupt pins available
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 ms
On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz
Power saving modes include Idle and Power-down
Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization
Processor wake-up from Power-down mode via external interrupt or BOD
Single power supply chip with POR and BOD circuits:
CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
BLOCK DIAGRAM:
PIN CONFIGURATION:
Pin Description:
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block.
P0.0/TXD0/PWM1:
P0.0 †General purpose input/output digital pin (GPIO)
TXD0 †Transmitter output for UART0
PWM1 †Pulse Width Modulator output 1
P0.1/RXD0/PWM3/EINT0:
P0.1 †General purpose input/output digital pin (GPIO)
RXD0 †Receiver input for UART0
PWM3 †Pulse Width Modulator output 3
EINT0 †External interrupt 0 input
P0.2/SCL0/ CAP0.0:
P0.2 †General purpose input/output digital pin (GPIO)
SCL0 †I2C0 clock input/output, open-drain output (for I2C-bus compliance)
CAP0.0 †Capture input for Timer 0, channel 0
P0.3/SDA0/ MAT0.0/EINT1:
P0.3 †General purpose input/output digital pin (GPIO)
SDA0 †I2C0 data input/output, open-drain output (for I2C-bus compliance)
MAT0.0 †Match output for Timer 0, channel 0
EINT1 †External interrupt 1 input
P0.4/SCK0/ CAP0.1/AD0.6
P0.4 †General purpose input/output digital pin (GPIO)
SCK0 †Serial clock for SPI0, SPI clock output from master or input to slave
CAP0.1 †Capture input for Timer 0, channel 0
AD0.6 †ADC 0, input 6.
P0.5/MISO0/ MAT0.1/AD0.7
P0.5 †General purpose input/output digital pin (GPIO)
MISO0 †Master In Slave OUT for SPI0, data input to SPI master or data output from
SPI slave.
MAT0.1 †Match output for Timer 0, channel 1
AD0.7 †ADC 0, input 7
P0.6/MOSI0/ CAP0.2/AD1.0
P0.6 †General purpose input/output digital pin (GPIO)
MOSI0 †Master out Slave In for SPI0, data output from SPI master or data
Input to SPI slave
CAP0.2 †Capture input for Timer 0, channel 2
AD1.0 †ADC 1, input 0, available in LPC2144/46/48 only
P0.7/SSEL0/PWM2/EINT2
P0.7 †General purpose input/output digital pin (GPIO)
SSEL0 †Slave Select for SPI0, selects the SPI interface as a slave
PWM2 †Pulse Width Modulator output 2
EINT2 †External interrupt 2 input
P0.8/TXD1/PWM4/AD1.1
P0.8 †General purpose input/output digital pin (GPIO)
TXD1 †Transmitter output for UART1
PWM4 †Pulse Width Modulator output 4
AD1.1 †ADC 1, input 1, available in LPC2144/46/48 only
P0.9/RXD1/ PWM6/EINT3:
P0.9 †General purpose input/output digital pin (GPIO)
RXD1 †Receiver input for UART1
PWM6 †Pulse Width Modulator output 6
EINT3 †External interrupt 3 input
P0.10/RTS1/ CAP1.0/AD1.2:
P0.10 †General purpose input/output digital pin (GPIO)
RTS1 †Request to send output for UART1, LPC2144/46/48 only
CAP1.0 †Capture input for Timer 1, channel 0
AD1.2 †ADC 1, input 2, available in LPC2144/46/48 only
P0.11/CTS1/ CAP1.1/SCL1:
P0.11 †General purpose input/output digital pin (GPIO)
CTS1 †Clear to send input for UART1, available in LPC2144/46/48 only
CAP1.1 †Capture input for Timer 1, channel 1
SCL1 †I2C1 clock input/output, open-drain output (for I2C-bus compliance)
P0.12/DSR1/MAT1.0/AD1.3:
P0.12 †General purpose input/output digital pin (GPIO)
DSR1 †Data Set Ready input for UART1, available in LPC2144/46/48 only
MAT1.0 †Match output for Timer 1, channel 0
AD1.3 †ADC input 3, available in LPC2144/46/48 only
P0.13/DTR1/ MAT1.1/AD1.4:
P0.13 †General purpose input/output digital pin (GPIO)
DTR1 †Data Terminal Ready output for UART1, LPC2144/46/48 only
MAT1.1 †Match output for Timer 1, channel 1
AD1.4 †ADC input 4, available in LPC2144/46/48 only
P0.14/DCD1/EINT1/SDA1:
P0.14 †General purpose input/output digital pin (GPIO)
DCD1 †Data Carrier Detect input for UART1, LPC2144/46/48 only
EINT1 †External interrupt 1 input
SDA1 †I2C1 data input/output, open-drain output (for I2C-bus compliance LOW on this pin while RESET is LOW forces on-chip boot loader to take over control of the part after reset
P0.15/RI1/ EINT2/AD1.5:
P0.15 †General purpose input/output digital pin (GPIO)
RI1 †Ring Indicator input for UART1, available in LPC2144/46/48 only
EINT2 †External interrupt 2 input
AD1.5 †ADC 1, input 5, available in LPC2144/46/48 only
P0.16/EINT0/MAT0.2/CAP0.2:
P0.16 †General purpose input/output digital pin (GPIO)
EINT0 †External interrupt 0 input
MAT0.2 †Match output for Timer 0, channel 2
CAP0.2 †Capture input for Timer 0, channel 2
P0.17/CAP1.2/ SCK1/MAT1.2:
P0.17 †General purpose input/output digital pin (GPIO)
CAP1.2 †Capture input for Timer 1, channel 2
SCK1 †Serial Clock for SSP, clock output from master or input to slave
MAT1.2 †Match output for Timer 1, channel 2
P0.18/CAP1.3/MISO1/MAT1.3:
P0.18 †General purpose input/output digital pin (GPIO)
CAP1.3 †Capture input for Timer 1, channel 3
MISO1 †Master In Slave Out for SSP, data input to SPI master or data output from SSP slave
MAT1.3 †Match output for Timer 1, channel 3
P0.19/MAT1.2/MOSI1/CAP1.2:
P0.19 †General purpose input/output digital pin (GPIO)
MAT1.2 †Match output for Timer 1, channel 2
MOSI1 †Master out Slave In for SSP, data output from SSP master or data Input to SSP slave
CAP1.2 †Capture input for Timer 1, channel 2
P0.20/MAT1.3/SSEL1/EINT3:
P0.20 †General purpose input/output digital pin (GPIO)
MAT1.3 †Match output for Timer 1, channel 3
SSEL1 †Slave Select for SSP, selects the SSP interface as a slave
EINT3 †External interrupt 3 input
P0.21/PWM5/AD1.6/CAP1.3:
P0.21 †General purpose input/output digital pin (GPIO)
PWM5 †Pulse Width Modulator output 5
AD1.6 †ADC 1, input 6, available in LPC2144/46/48 only
CAP1.3 †Capture input for Timer 1, channel 3
P0.22/AD1.7/CAP0.0/MAT0.0:
P0.22 †General purpose input/output digital pin (GPIO)
AD1.7 †ADC 1, input 7, available in LPC2144/46/48 only
CAP0.0 †Capture input for Timer 0, channel 0
MAT0.0 †Match output for Timer 0, channel 0
P0.23/VBUS:
P0.23 †General purpose input/output digital pin (GPIO)
VBUS †Indicates the presence of USB bus power
This signal must be HIGH for USB reset to occur
P0.25/AD0.4/AOUT:
P0.25 †General purpose input/output digital pin (GPIO)
AD0.4 †ADC 0, input 4
AOUT †DAC output, available in LPC2142/44/46/48 only
P0.28/AD0.1/CAP0.2/MAT0.2:
P0.28 †General purpose input/output digital pin (GPIO)
AD0.1 †ADC 0, input 1
CAP0.2 †Capture input for Timer 0, channel 2
MAT0.2 †Match output for Timer 0, channel 2
P0.29/AD0.2/CAP0.3/MAT0.3:
P0.29 †General purpose input/output digital pin (GPIO)
AD0.2 †ADC 0, input 2
CAP0.3 †Capture input for Timer 0, Channel 3
MAT0.3 †Match output for Timer 0, channel 3
P0.30/AD0.3/EINT3/CAP0.0:
P0.30 †General purpose input/output digital pin (GPIO)
AD0.3 †ADC 0, input 3
EINT3 †External interrupt 3 input
CAP0.0 †Capture input for Timer 0, channel 0
P0.31/UP_LED/CONNECT
P0.31 †General purpose output only digital pin (GPO)
UP_LED †USB Good Link LED indicator, it is LOW when device is configured (non-control endpoints enabled), it is HIGH when the device is not configured or during global suspend
CONNECT †Signal used to switch an external 1.5 kohms resistor under the
Software control, used with the Soft Connect USB feature
Important: This is a digital output only pin, this pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit, the operation of port 1 pins depends upon the pin function selected via the pin connect block, pins 0 through 15 of port 1 are not
Available.
P1.16/TRACEPKT0
P1.16 †General purpose input/output digital pin (GPIO)
TRACEPKT0 †Trace Packet, bit 0, standard I/O port with internal pull-up
P1.17/TRACEPKT1
P1.17 †General purpose input/output digital pin (GPIO)
TRACEPKT1 †Trace Packet, bit 1, standard I/O port with internal pull-up
P1.18/TRACEPKT2
P1.18 †General purpose input/output digital pin (GPIO)
TRACEPKT2 †Trace Packet, bit 2, standard I/O port with internal pull-up
P1.19/TRACEPKT3
P1.19 †General purpose input/output digital pin (GPIO)
TRACEPKT3 †Trace Packet, bit 3, standard I/O port with internal pull-up
P1.20/TRACESYNC
P1.20 †General purpose input/output digital pin (GPIO)
TRACESYNC †Trace Synchronization, standard I/O port with internal pull-up
Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset
P1.21/PIPESTAT0
P1.21 †General purpose input/output digital pin (GPIO)
PIPESTAT0 †Pipeline Status, bit 0, standard I/O port with internal pull-up
P1.22/PIPESTAT1
P1.22 †General purpose input/output digital pin (GPIO)
PIPESTAT1 †Pipeline Status, bit 1, standard I/O port with internal pull-up
P1.23/PIPESTAT2
P1.23 †General purpose input/output digital pin (GPIO)
PIPESTAT2 †Pipeline Status, bit 2, standard I/O port with internal pull-up
P1.24/TRACECLK
P1.24 †General purpose input/output digital pin (GPIO)
TRACECLK †Trace Clock, standard I/O port with internal pull-up
P1.25/EXTIN0
P1.25 †General purpose input/output digital pin (GPIO)
EXTIN0 †External Trigger Input, standard I/O with internal pull-up
P1.26/RTCK
P1.26 †General purpose input/output digital pin (GPIO)
RTCK †Returned Test Clock output, extra signal added to the JTAG port, assists debugger synchronization when processor frequency varies, bidirectional pin with internal pull-up
Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate a Debug port after reset
P1.27/TDO
P1.27 †General purpose input/output digital pin (GPIO)
TDO †Test Data out for JTAG interface
P1.28/TDI
P1.28 †General purpose input/output digital pin (GPIO)
TDI †Test Data in for JTAG interface
P1.29/TCK
P1.29 †General purpose input/output digital pin (GPIO)
TCK †Test Clock for JTAG interface
P1.30/TMS
P1.30 †General purpose input/output digital pin (GPIO)
TMS †Test Mode Select for JTAG interface
P1.31/TRST
P1.31 †General purpose input/output digital pin (GPIO)
TRST †Test Reset for JTAG interface
D+: USB bidirectional D+ line
D- : USB bidirectional D- line
RESET External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0, TTL with hysteretic, 5 V tolerant
XTAL1: Input to the oscillator circuit and internal clock generator circuits
XTAL2: Output from the oscillator amplifier
RTCX1: I Input to the RTC oscillator circuit
RTCX2: Output from the RTC oscillator circuit
VSS: 6, 18, 25, 42, 50 pins are for supply voltage.
Ground: 0 V reference.
VSSA Analog ground: 0 V reference, this should nominally be the same voltage as
VSS, but should be isolated to minimize noise and error
VDD 23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O ports.
VDDA 7 I Analog 3.3 V power supply: This should be nominally the same voltage as
VDD but should be isolated to minimize noise and error, this voltage is only used to power the on-chip ADC(s) and DAC
VREF ADC reference voltage: This should be nominally less than or equal to the
VDD voltage but should be isolated to minimize noise and error, level on this
Pin is used as a reference for ADC(s) and DAC
VBAT RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC.
Functional Description:
Architectural Overview:
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
And impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set.
Essentially, the ARM7TDMI-S processor has two instruction sets:
¢ The standard 32-bit ARM set
¢ A 16-bit Thumb set
The Thumb setâ„¢s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARMâ„¢s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode.
On-Chip Flash Program memory:
The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for userâ„¢s code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.
The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention.
On-Chip Static RAM:
On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution.
Memory Map
The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown below.
Interrupt controller:
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
Fast interrupt request (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
Interrupt Sources:
Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Pin Connect Block:
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined.
The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 and Port 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain.
Fast General purpose Parallel I/O:
Device pins that are not connected to a specific
