25-03-2015, 10:49 PM
Vhdl code to design jk flip flop using NAND gate
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jk flip flop using nand gate
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Vhdl code to design jk flip flop using NAND gate
20-03-2017, 04:38 PM
The JK flip-flop is also called programmable flip-flop because, using its inputs, J, K, S and R, can be made to mimic the action of any of the other types of flip-flops.
Operation
As a starting point, suppose that both J and K are in logic 1 and the outputs Q = 0 and Q = 1, this will make NAND 1 enabled, since it has 1 logic in two (J and Q) of its three , Requiring only a logic 1 on its clock input to change its output state to logic 0. At the same time, NAND 2 is disabled, because it only has one of its inputs (K) in logic 1, its feedback input is In Logic 0 due to feedback from Q.
On the arrival of a clock pulse, the NAND output 1 thus becomes logic 0, and causes the flip-flop to change state so that Q = 1 and Q = 0. This action allows NAND 2 and disables NAND 1 .
![[Image: JK-basic.gif]](http://www.learnabout-electronics.org/Digital/images/JK-basic.gif)
As this change of state in the outputs occurs however, there is a problem. If the clock pulse continues to be high, or in its time period when the flip-flop changes state, the NAND 2 output will instantly go to logical 0 and the flip-flop will return to its original state. This can then configure a situation in which the flip-flop will oscillate rapidly between its two states.
![[Image: JK-MS-symbol.gif]](http://www.learnabout-electronics.org/Digital/images/JK-MS-symbol.gif)
![[Image: seq13.gif?x98918]](http://www.electronics-tutorials.ws/sequential/seq13.gif?x98918)
These problems caused by the output data 'running' around the feedback lines from the output to the input before the end of the clock pulse are known as DANGERS OF REASON and of course should be avoided. This can be done however using a more complex version of the circuit.
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