INTER INTEGRATED CIRCUIT BUS CONTROLLER


The I2C stands for Inter Integrated circuit helps in establishing short distance communication between ICs. The communication takes place in accordance with the Philips I2C bus protocol.

In todayâ„¢s highly complex circuits, I2C plays a major role in reducing the interconnection complexity between the ICs.

I2C bus is a 2 wire bi-directional serial bus. One wire is for data transmission named as Serial data bus (SDA) and the other for clock signal transmission (SCL). These carry information between the devices connected to the bus.

I2C is easy to use to page link multiple devices together since it has built in addressing scheme.

Our project aim involves the design of both master and slave cores. The master core is responsible for initiating the communication on the bus. The slave core is the device that has been addressed by the master in order to establish effective communication. Each slave has a unique address and responds only after it has verified the address sent by the master. I2C is a true multi master bus; this means that more than one master can attempt to control the bus at the same time without corrupting the message. This is achieved by a technique known as arbitration, where if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted.

Another concept known as clock synchronization is used in order to synchronize clock signals of two or more devices. It is performed using the wired-AND connection of I2C interface to SCL line. Devices with shorter LOW periods enter a HIGH wait-state during this time.

The RTL code for the design has been done using Verilog HDL. The functional verification has been done using ModelSim and the code has been synthesized using Xilinx ISE. This has been finally implemented onto a FPGA Spartan IIE kit.