IMPLANTABLE STIMULATOR WITHOUT OFF-CHIP CAPACITOR
SEMINAR REPORT
Submitted by
SHIYAD ASHARAF
B.Tech
Applied Electronics and Instrumentation
Seventh Semester
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COLLEGE OF ENGINEERING
TRIVANDRUM 2010
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1. INTRODUCTION
For a patient suffering from spinal cord injury, the normal direct control of the lower limbs by the brain is lost. However, most of the nerves and muscles below the injury are not affected and can be used if artificially stimulated by means of functional electrical stimulation (FES). For example, it has been demonstrated that leg muscle function, and bladder-emptying can be restored by applying trains of stimulation current pulses which cause appropriate muscles to contract. Usually, each stimulation pulse consists of a cathodic phase followed by an anodic phase. In the cathodic phase, the stimulus current depolarizes nearby axons and initiates the action potential which elicits the muscle response. The succeeding anodic phase cancels the charge accumulated in the cathodic phase on the electrodes. Sometimes an inter-phase delay separates the two stimulation phases slightly so that the anodic phase does not block action potential propagation initiated by the cathodic phase. Usually the leading cathodic phase is active (square pulse) while the following anodic phase can be either active (square pulse) or passive (exponential decay).
The design of neural stimulators for implantable FES systems has over the years benefited from advances in microelectronics and packaging technology. Early designs used discrete components, but even now (Fig.1) discrete blocking-capacitors are still widely used to ensure adequate safety. Safety is of prime concern because electrodes that are meant for stimulation could, under faulty conditions, electrolyze water or cause other toxic effects in the tissue causing serious injury. The danger is usually diminished and made acceptable by placing a capacitor in series with each stimulating electrode. The blocking-capacitor limits the charge on the electrodes to Qmax=C.V where C is the capacitance and V is (usually) the power supply voltage. Qmax should be chosen so that the charge density cannot exceed the safety limit which depends on the electrode material. Typically, for FES applications these capacitors are in the order of a few microfarad each; not physically small components that could be integrated on silicon with the rest of the stimulator circuitry. Thus, the physical size of multichannel implantable stimulators for FES systems is often determined by the off-chip blocking-capacitors (Fig.1). This is a serious limitation for developing implants with a large number of stimulating channels for finer interaction with the nervous system. Such stimulators would allow selective stimulation of smaller nerve fibre groups in, for example, the lower motor nerves, which could lead to more natural control of movement of paralyzed muscles.
Fig.1
Apart from protection against electrolysis following semiconductor failure, the use of blocking-capacitors provides a simple solution to maintaining charge-balance during normal stimulation. However, this can also be achieved by relying on the capacitive property of polarisable electrodes such as porous platinum (Pt) or iridium oxide with passive discharging. This method is utilized in the stimulator output stage circuit presented in this paper. A recent paper has reported a blocking-capacitor-free stimulator that achieves very precise charge-balanced active biphasic stimulation implemented in a standard CMOS technology. However, unlike the stimulator chip described in this paper, the stimulator chip in cannot be guaranteed fail-safe under single-fault conditions.
There are other methods of protection that do not utilize blocking-capacitors, including continuous monitoring of the electrode-tissue impedance the stimulus current level or the electrode voltage. The recorded values are continuously compared with a predefined reference, which when exceeded, inhibits the stimulator output stage to prevent nerve damage. The advantage of this approach is volume saving because the monitoring circuit can be integrated with the stimulator output stage circuit. However, the monitoring circuit increases the stimulator output stage complexity, which itself increases the likelihood of semiconductor failure.
It should be noted that electrostatic discharge (ESD) protection at all I/O pads of the stimulator chip is an important requirement for safe handling and is especially necessary for the pads connecting to the stimulating electrodes. Usually, the standard I/O pads from the technology provider can be used, as was the case for the stimulator chip in this paper. However, for applications requiring many stimulating channels, e.g., retinal prosthesis, the area of the standard I/O pads may be too large to meet the constraints of the available physical space. A compact custom-made ESD cell can be found in.
In this paper, we present a neural stimulator with an output stage (electrode driving circuit) that is fail-safe under single fault conditions without the need for off-chip blocking-capacitors. In order to miniaturize the stimulator output stage two novel techniques are introduced. The first technique is a new current generator circuit that reduces to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption compared to previous works. The current generator uses voltage-controlled MOS resistors in the deep triode region and features high linearity, small voltage compliance1 and high output impedance. It is also more compact than previous current generator circuits used in implantable neural stimulators and its linearity performance is not affected by mobility reduction. The second technique is a new stimulator output stage circuit with blocking-capacitor safety protection that utilizes our high-frequency cur-rent-switching (HFCS) technique and passive discharging. Unlike conventional stimulator output stage circuits for implantable FES systems which require blocking-capacitors in the microfarad range, our proposed approach enables capacitance reduction to the picofarad range pF . Hence, the complete stimulator can be integrated on a single silicon chip and still be fail-safe. The prototype four-channel neural stimulator chip was fabricated in XFAB’s 1- m silicon-on-insulator (SOI) CMOS technology. We obtained successful recordings of action potentials and a strength-duration curve from the sciatic nerve of a frog with our stimulator which demonstrates the practicality of stimulating real nerve by the HFCS technique.
The remaining sections of the paper are organized as follows. Section II describes three conventional stimulator output stage circuits with blocking-capacitors and presents an overview of previous work on the design of current generator circuits for implantable neural stimulation. Section III describes the new current generator circuit (for a 4-bit implementation) and Section IV explains the HFCS technique and presents the new stimulator output stage circuit. The architecture of the fabricated stimulator including measured results and the in vitro experiments are presented in Section V. Finally, Section VI concludes the paper by summarizing our contributions.
2. OVERVIEW
2.1 Stimulator Output Stages Utilizing Blocking-Capacitors
Fig. 2 shows three commonly used stimulator output stage configurations each employing a blocking-capacitor for two electrode setup: (a) dual supplies with both active phases, (b) single supply with both active phases and © single supply with active cathodic phase and passive anodic phase. The nerve tissue sits between the anodic (A) and the cathodic © electrodes; this polarity refers to the stimulus pulse. For the configuration in Fig.2(a), the cathodic electrode is always connected to a reference voltage, usually the midpoint of the two supply voltages. The programmable current sink IstimC and current source IstimA generate the cathodic and anodic currents, respectively. These currents are driven through the load, ZL representing the nerve-electrode impedance, by the control of switches S1 and S2 When only a single supply is available [Fig.2(b)], the anodic and cathodic currents are generated from a single current sink (Istim) by reversing the current paths using switches S2.
Fig.2
Both configurations in Fig.2(a) and (b) are (ideally) designed to be charge-balanced to avoid charge accumulation. However, achieving exactly zero net charge after each stimulation cycle is not possible due to mismatch in the current source and sink drivers or due to timing errors and leakage from adjacent stimulus sites. Therefore, periodic removal of the residual charge is necessary using switch S3 which provides an extra passive discharging phase. During this extra phase the voltage on the blocking-capacitor drives current through the electrodes to fully discharge them. Given the necessity for the third phase in the circuits of Fig.2(a) and (b), some designers use the passive discharging phase as the main anodic phase, as shown in the circuit of Fig.2©. Passive discharging is easily implemented but the discharging phase must be long enough.
As mentioned in Section I, the voltage on the electrode capacitance can also drive the passive discharging current. However, blocking-capacitors may still be considered necessary to ensure that direct current cannot flow if the electrodes are charged beyond their capacitive range (“water window”) due to semiconductor or other fault. Various mechanisms of semiconductor failure in stimulators either implanted or under accelerated tests have been reported. These include short-circuit due to moisture penetration into the glass seal of the silicon package, gate-oxide breakdown and change of device parameters after implantation, for example, due to ionizing radiation.
2.2 Current Generator Circuits
Several current generator circuits for implantable neural stimulators have been reported in the literature. The full-scale output current varies from about 100 A to 16 mA and the resolution from 3 to 8 bits, depending on the application. Desirable features for a current generator circuit for use in this application are small voltage compliance, high output impedance, good linearity, low power consumption and small silicon area.
A current mirror is probably the easiest way to duplicate or scale the current-mode digital-to-analog converter (DAC) output current, IDAC to the output current, I out through the load ZL, as shown in Fig.3(a). However, both IDAC to the output current, I out branches consume power from the supplies. Although the power consumed by the IDAC branch is only 1/n (usually, n>1) of the power consumed by the I out branch, it could be completely saved by moving the DAC in series with the load, keeping one branch only, as shown in Fig.3(b). By doing so, the DAC is functionally a current generator. Usually, an n-bit current-mode DAC is composed of n binary-weighted transistors whose gates are connected to a common bias voltage. However, it is also possible to employ identical transistors with “binary-weighted bias voltages”.
In practice, the DAC current sink (or source) transistors are cascoded to increase the output impedance to maintain a constant output current, regardless of the voltage variation across the load. The cascode transistor is usually biased by a static voltage while it is also possible to increase the DAC output impedance by biasing the cascode transistor with active feedback. In Fig. 4, the high-gain amplifier locks the drain voltage of M2 to be equal to the drain voltage of M1 (i.e., the amplifier acts as a voltage follower). The same biasing conditions make the drain current of M2 n times the current of M1 the same as their aspect ratio difference. The output impedance of the active feedback current generator is given by
Rout = Agm4r4r
Where A is the amplifier gain, ris the output resistance of and gm and r 4 are the transconductance and output resistance of M4, respectively. The output impedance is Rout= Agm4r4rtimes larger than that of only. It is also possible to achieve an adjustable current generator by using a voltage follower to bias a fixed resistor, as shown in Fig.5. The input of the voltage follower, which is also the bias voltage across the resistor, is programmed by the DAC. The output current is given by
Iout = VDAC/R (2)
Where VDAC is the output voltage of the DAC and is R the fixed resistance. However, controlling Iout by changing VDAC is not desirable because it changes the voltage compliance of the current generator circuit.
Fig.5
It is known from (2) that the output current is also reciprocally proportional to the resistance. Thus, a voltage-controlled resistor with a constant bias will also make a current generator. The voltage-controlled resistor is usually implemented by a MOS transistor in the triode region, as shown in Fig.6. This configuration yields a current generator circuit with small voltage compliance. When the bias voltage Vref is small, in the order of several hundred millivolts, M1 operates in deep triode region and its drain current may be given by
ID1 = CoxW1/L1(VDAC-VT)Vref (3)
which represents a linear resistor between the drain-source terminals equal to
RDS1 = 1/ CoxW1/L1(VDAC-VT) (4)
Where is the mobility, Cox is the oxide capacitance per unit area, VT is the threshold voltage and W1 and L1 are the width and length of transistor M1, respectively. However, at large gate-source voltages, mobility degradation due to the high vertical field cannot be neglected. To model this effect, the effective mobility is changed to
eff = 0/1+ (VDAC-VT) (5)
Where 0 is the low-field mobility and is a fitting parameter roughly equal to 10-7/toxV-1 (is oxide thickness); for the approximation in (5) only the first two terms of the Taylor series expansion were retained. Because of the mobility degradation, the drain current will not be very linear to the overdrive voltage(VDAC-VT) , especially for VDAC values controlled by the most significant bits (MSBs) of the DAC. To reduce nonlinearity, an extra current compensation circuit operating in the saturation region was employed in at the expense of higher complexity and power consumption.
Fig.6
3. PROPOSED CURRENT GENERATOR CIRCUIT
All the current generator circuits described in Section II need at least two steps to translate the digital input bits into the output current. For both implementations of binary-weighted transistors with single bias and of identical transistors with binary weighted bias, the digital input bits control the gates of the DAC current source or sink transistors to be either a fixed bias voltage or 0 V. The bias voltages then drive the DAC transistors to generate the output current. For the implementations of active feedback, voltage follower and voltage-controlled resistor, the digital input bits are first translated into an analog voltage which is subsequently used to bias a resistor or a transistor in order to generate the output current.
In this paper, we propose a new current generator circuit which requires only one step to translate the digital input bits into the output current. The circuit schematic is shown in Fig. 7 for a 4-bit implementation. The circuit is based on the topology of the voltage-controlled resistor and is still implemented by MOS transistors in the deep triode region for small voltage compliance. The main difference between the proposed circuit and previous works is that the digital input bits are loaded directly onto the corresponding binary-weighted current sink transistors (implemented as unit transistors). Therefore, unlike the voltage-controlled MOS resistor implementation in 26] where the gate voltages of the current sink transistors are analog, sweeping from VT to the full-swing of VDAC, the gate voltages of all current sink transistors (M1-M2) in the proposed circuit are 1-bit digital; VDD (positive digital supply rail) for hard on and 0 V (negative digital supply rail) for hard off. Therefore, the digital input bits in Fig.7 are not only the enable/disable signals, but also the driving signals for current generation.
Fig.7
When the circuit is on, the transistor gate-source voltage is VDD, which will cause maximum mobility degradation. Since VDD is the exclusive option in order to generate any output current, all current sink transistors exhibit the same mobility degradation (this is not the case with the circuit in). The drain current of each unit transistor (of aspect ratio W/L) may be calculated using (3) and (5) by
ID = oCoxW/L[(VDD-V)-[(VDD-VT)2].Vref (6)
For a 4-bit implementation, the output current may be expressed by
IOUT = (d020+d121+d222+d323) x { oCoxW/L[(VDD-V)-[(VDD-VT)2].Vref (7)
Where di equals 1 or 0; d0 is the least-significant-bit (LSB) and d3 is the MSB. From (7) it can be seen that unlike the analog-based DAC in, mobility degradation does not affect the linearity performance of the proposed DAC implementation; it only causes a small gain error which is insignificant for this application. An additional advantage of the proposed circuit is that no analog biasing or linearity compensation circuits are required. This greatly reduces complexity, which in turn minimizes silicon area and power consumption.
4. FAIL-SAFE STIMULATOR OUTPUT STAGE
4.1 HFCS Technique
The value of the blocking-capacitor depends on the requirement for a specific stimulation. For example, to recover partial leg movements, stimulus currents of about 1 mA intensity and 1 ms pulsewidth, are required. The aim is to minimize the voltage “wasted” across the blocking-capacitor so that most of the power supply voltage can be made available to the load. To calculate the required capacitance, the following elementary equation may be used
C = Istim t/V (8)
Where Istim is the stimulus current amplitude, t is the stimulus current pulsewidth and V is the change in voltage across the blocking-capacitor during stimulation. For the above numerical example, to limit the capacitor voltage drop, to say 0.5 V, a 2F capacitor is required. Clearly, such a large capacitor is impractical to implement on silicon due to large area and cost requirements, thus the use of off-chip surface mount capacitors (Fig.1). The blocking-capacitor value may be reduced at the expense of a larger voltage drop across it, but this will result in a higher supply voltage.
From (8), with constant Istim andV, the capacitor value is proportional to the time the stimulus current flows through it. Thus, shorter charging periods lead to a smaller blocking-capacitor. For example, if the 1 mA stimulus current consists of a train of 50 ns pulses (i.e., the changing time is limited to 50 ns), only a 100 pF capacitor is required for 0.5 V drop across it. The idea behind the HFCS technique is llustrated by the timing waveforms in Fig. 8(b) and ©, where the active cathodic phase in Fig.8(a) is generated by the summation of two high-frequency complementary current pulses IS1, and IS2, each with a pulsewidth of 50 ns. In Fig.8(a) the electrode is actively charged (controlled current) in phase A and B passively discharged in phase (current driven by voltage across capacitor which can be the capacitance of the electrode itself). For charge-balance, the areas under A and B must be equal and this is achieved by making the passive anodic phase much longer than TCATHODIC.
Fig.8
4.2 Proposed Output Stage
Fig. 9 shows the simplified schematic of the proposed stimulator output stage circuit utilizing HFCS and passive discharging. The circuit uses two small blocking-capacitors ( C1 and C2 ), one for the IS1 current branch and the other for the IS2 current branch. The timing waveforms in the same figure control switches S1-S4 and S4.
The operation of the circuit is as follows. During clock phase 1, for the IS1 branch, S1 is closed and S3 is open. The load switch SL is also open. In this phase, diode D1 is reverse-biased and D2 diode is forward-biased. The constant current Istim (generated by the programmable current generator circuit in Fig.7) flows through C1 (charging it up) and D2, forming current IS1 through the load. In the same phase, for IS2 the current branch, S2 is open and D3, S4 and C2 form a closed path which discharges C2 to one diode drop voltage. During clock phase 2, for the branch IS2, S2 is closed, S4 is open, D3 is reverse-biased and D4 is forward-biased. Current Istim flows through C2 (charging it up) and D4, forming current IS2 through the load. In the same phase, for the IS1 current branch, S1 is open and D1, S3 and C1 form a closed path which discharges C1 to one diode drop voltage. The alternating charging and discharging of the two blocking-capacitors continues in this manner for the entire length of the cathodic phase (TCATHODIC )and the summation of the high-frequency currents IS1 and IS2 results in the long cathodic current through the load [see Fig.8(a)]. During clock phase 3, the load switch SL is closed (all other switches are open) and the load is passively discharged. Switches S1 and S2 may be implemented with nMOS transistors while switches S3, S4 and SL with pMOS transistors.
Fig.9
Implanted devices for chronic use in patients should be failsafe under single-fault conditions; it is considered extremely unlikely that more than one device failure will occur at one time (provided faults are independent). The proposed output stage circuit conforms to this requirement provided that it is implemented in a technology which supports fully floating diodes and capacitors and isolated transistors. This is possible in a deep trench isolated SOI CMOS technology. Under single-fault conditions (assuming SOI CMOS implementation), Table I summarizes the outcome if a circuit component fails as a short or open circuit. A component failure would render the output stage less functional for stimulation purposes. However, the importance here is that a single component failure cannot cause prolonged direct current flow to the stimulation load, so that electrolysis cannot happen. Note that in the proposed circuit, the load is dc-connected to a single voltage (VDDA; positive analog supply rail) only. Hence, in the event of either D1 or D2 or D3 or failing, no prolonged direct current can flow to the load because of the absence of a complete dc path. It should be noted that any failure in the circuit section before the blocking-capacitors [grey area in Fig. 9(a)] is not dangerous because of C1 and C2.
Switch SL should be realized as multiple isolated transistors in parallel for ample redundancy. In addition, the gates of these multiple transistors must be ac-coupled from the driver circuit to cater for the unlikely event of gate-oxide breakdown which would short the gates to the dc supply rails.2 The deep trench isolated SOI CMOS technology we used for this work is ideal for realizing fully-isolated, passive and active devices that are also isolated from the substrate by a thick buried oxide layer. Hence, in the event of one device failing, it is very unlikely that this will trigger the failure of other devices as a chain reaction.
Fig. 10 shows the proposed ac-coupled arrangement for switch SL. When the load is being stimulated (active cathodic phase) clock signal 1 is sitting at 5 V (positive digital supply rail). When the load discharging is initiated, 4 becomes an oscillating signal operating between 0 and 5 V (digital supply). When 4 is 5 V the voltage at VB is the analog VDDA because of resistor R1. When 4 suddenly becomes 0 V, the current flows in the direction of VDDA C4 D5 C3 and the voltage at VA , initially drops down to approximately VDDA+VTD6-5V (VTD6 is the threshold voltage of the forward biased diode D6) and VB to VDDA + VTD6 -5V+ VTD5 ( VTD5 is the threshold voltage of the forward biased diode D6 ). Transistor ML begins to conduct because of a source-gate voltage (VSG) larger than VTL (VTL is the threshold voltage of ML). However, the of decreases with time, preventing from further conducting. The voltage at will finally reach again by the path provided by. The recovery time is governed by the time-constant. In order to maintain a low voltage level at, needs to absorb more energy from than that consumed by . Thus, the period of the oscillating has to be smaller than the time-constant (in a time interval of, 10% of the voltage across is recovered by). It is important that at the end of each driving pulse, the is still larger than in order to maintain the conduction of ML. In Fig. 10, R1=250ke, C4=5pF and C3=10dpF.
5. MEASURED RESULTS
A four-channel stimulator employing the 4-bit current generator and the output stage circuit described respectively in Section III and Section IV-B, was fabricated in the XFAB’s 1- m SOI CMOS technology.3 The functional block diagram of the stimulator is shown in Fig. 11. It consists of the 4-bit current generator (DAC), two voltage-controlled oscillators (VCOs), a high-voltage charge pump, some digital control logic and the electrode driving circuit (four output channels). The current generator is multiplexed between the four output stages. The VCOs are based on the ring oscillator topology; VCO-1 provides the switching frequency of the charge pump and VCO-2 provides the switching frequency of the output stages. The frequency of VCO-1 can be adjusted between 5 and 50 MHz depending on the power requirements, while the frequency of VCO-2 can be varied between 1 and 20 MHz. The charge pump is based on the classic Dickson topology. Four stages are used to pump from 5 V to a high voltage (up to about 18 V). The inter-stage capacitors of the charge pump are 28 pF each and a 1 nF external capacitor is used for storage. The proposed output stage requires about 2.5 V across it and the rest of the VDDA is available for the load.
Fig.11
The stimulator chip microphotograph is shown in Fig.12. Each of the four output stages contains 2x100 pF blocking-capacitors. An additional test-structure output stage was included for testing the fail-safe operation of the circuit under single-fault solutions (to imitate the failure conditions listed in Table I). In total 20 chips were fabricated with 100% yield. The breakdown of the silicon area and power consumption usage is shown in Table II.
Fig.12
5.1 Current Generator Circuit
The binary-weighted transistors in the 4-bit DAC were laid out with unit transistors in common-centroid structure, with dummies at the periphery for better matching. The DAC digital input codes were set to either 0 or 5 V (digital supply). The amplifier in Fig.7 was a pMOS-input folded cascode amplifier with a dc gain of 72 dB, a unity gain bandwidth of 9 MHz and a slew-rate of 8.33 V s. The amplifier was compensated by a 4 pF capacitor at its output node and was stable for all values of the stimulating current. The area of the 4-bit DAC as noted in Table II is 0.09 mm, 83% of which is occupied by the amplifier.
The bias voltage Vref was not included in the prototype chip and was provided externally. However, a supply-independent and temperature-independent bias circuit can be easily designed. With a Vref of 176 mV at the noninverting input of the amplifier, the measured drain-source resistance of the unity transistors is in the range of 2.59-2.71 k across all chips. Fig. 13 shows the 4-bit current generator output current versus DAC digital input for three settings. The integral nonlinearity (INL) and differential nonlinearity (DNL) of the DAC for the case of 1 mA full-scale current, is shown in Fig.14. The maximum INL error is only 0.065 LSB while the maximum DNL error is only 0.032 LSB. It is also possible to change the output current by keeping the digital input constant and changing. Fig.15 shows the output current versus for the digital input code 1111. The onlinearity, calculated by the method described in, is only 1.25% over the entire range.
The output characteristic of the current generator is shown in Fig. 16 for the DAC input codes 0011, 0111 and 1111 (all for mV). The curves show that the circuit requires only 0.22 V, 0.28 V and 0.41 V across its output to respectively maintain constant currents of 200 A, 466.7 A and 1 mA. The circuit in requires about 0.7 V to maintain a constant current of 200 A. This demonstrates that the proposed current generator circuit has indeed very small voltage compliance even for currents in the milliampere range. The output impedance of the circuit is above the accuracy of the measurement equipment. Cadence Spectre simulations indicate that the output impedance is approximately 100 M at 1 mA and remains greater than 40 M for an output voltage as low as 0.6 V.
The temperature coefficient of the output current (for 1 mA full-scale current) in simulation is 4.4 A C. However, temperature effects are less important for an implanted device due to the stable temperature conditions in the body [21]. The proposed current generator circuit requires a well regulated digital supply voltage (VDD) for driving the gates of the DAC transistors. The sensitivity of the output current to VDD variation (for 1 mA full-scale current) in simulation is about 150 nA/mV. For VDD=5V, all fabricated samples showed no more than 1% deviation from the nominal 1 mA full-scale output current. Although analog mismatch, temperature and digital supply variations cause some deviation of the output current from its nominal value, this is not important because in our application (stimulation of the lumbo-sacral nerve roots which can be used to restore lower-body function to paraplegics after spinal cord injury) we can compensate for it by fine control of the pulsewidth (in 10 s steps) of the active cathodic current.
Since the proposed current generator circuit achieves high linearity without any biasing or compensation circuits, it is very area-efficient. Table III compares the performance of various neural stimulator current generator circuits (assuming 4-bit implementation) in terms of linearity, voltage compliance, output impedance and silicon area. The proposed circuit is the best option where high linearity, small voltage compliance and small silicon area are of prime importance.
5.2 Output Stage With HFCS
The output stage was first tested with various RC load combinations with impedances between 1 and 10 k. For the larger loads, the internal charge pump was used to provide the analog power supply (VDDA). Fig.17 shows the measured current and voltage waveforms for a series RC load (8 ke+300nF) for two complete stimulation cycles. The repetition rate was 25 Hz with 1 ms active cathodic phase, 1 ms inter-phase delay (between the cathodic phase and the anodic phase) and 37 ms passive anodic phase. The current from the current generator was set to 1 mA. For this measurement the output of the charge pump was about 15 V.
Fig.17
As another illustration, Fig.18 shows the measured voltage across a series 500e+1F load (the impedance of this combination is similar to that of a book electrode). An external 6 V power supply (i.e., VDDA=6V) was used for this measurement since using the internal 4-stage charge pump for smaller than 10 V was not efficient. The timing profile was kept the same as that in Fig. 17. The amplitude of the active cathodic current was kept at 1 mA while the amplitude of the initial passive anodic current was limited to 100%, 40%, and 20% of the amplitude of the cathodic current, respectively, by appropriate dimensioning of the discharging transistor (ML)or by an external resistor (of an appropriate value) in series with the discharging transistor. A small discharging current would be the case in practice to ensure that stimulation does not occur in the second phase. As shown in the figure, the smaller the discharging current, the longer it takes to discharge.
Fig.18
Fig.19 shows the operation of the proposed ac-coupled technique for the load discharging switch. For testing, a 10 k resistor was connected at node VC in Fig. 10. The other end of the resistor was connected to the negative supply (0 V). The voltage waveforms 4 and VC are shown, respectively, in Fig. 18 (for VDDA=6V). When the 1 MHz oscillating signal is applied at 4, transistor ML conducts. Thus, the ON level of VC is close to VDDA [see Fig. 18(b)]. The slight difference is caused by the drain-source voltage drop of ML. Each output stage circuit (consists of HFCS stage and ac-coupled discharging circuit) occupies an area of 0.38 mm2.
Fig.19
Fig.20 shows the measured voltage waveforms across the blocking-capacitor (C1 or C2 in Fig. 9) for different switching frequencies f at 0.5 mA stimulation. These waveforms were obtained using on-chip buffers. The voltage drop across each blocking-capacitor is proportional to the period of the high-frequency signal and is independent of the duration of the complete active cathodic phase. As seen in the figure, 20 MHz results in approximately 3 times less voltage drop across the blocking-capacitor than 7 MHz. However, it can be shown that there is an optimized switching frequency for minimal power consumption due to the energy used to charge and discharge the two small blocking-capacitors and the dynamic power of the switching action of the four switches (S1-S4 in Fig. 9). The optimized frequency to achieve minimum power consumption in the stimulation phase (assuming ideal diodes with no stray capacitance) is given by
foptimum2 = Istim2/2CiCgVg2 (9)
Where Ci is the small blocking-capacitor (C1 or C2) and Cg and Vg are respectively the total capacitance and the voltage pulse amplitute at the gates of the four switches (S1-S4) in Fig. 9. In the fabricated stimulator, Ci =100pF, Cg=1.92pF (480 fF per switch) Vg=5V and so for Istim=1mA, the foptimum using is 10.2 MHz.
Fig.20
5.3 Testing of Single-Fault Failures
The fail-safe operation of the stimulator output stage under single-fault conditions has been both simulated and measured with an on-chip test structure in which extra switches have been added in series and in parallel with the components listed in Table IV. Because of the symmetrical structure of the proposed output stage circuit, only failures in the left branch are presented. As shown in Table IV, for all failures the output current is never more than the current in normal operation. The measured current is higher than the estimation when it is expected to be 50% due to the limited slew-rate of the current generator amplifier which is not able to fully switch on and off at this speed. As a result, the current generator pushes more than half the proper current into the load when only one half of the circuit is functional.
5.4 Measurement of Direct Current in Vitro
Fig. 21 shows the setup used to measure the direct current flowing from the stimulator through a dipole book electrode in a saline bath (0.9% saline). The method was adopted from [11]. In the figure, Rlimit, R1, CAC and RDC are off-chip components added for the test. is an external resistance box used to adjust the amplitude of the initial current in the passive discharging phase to some ratio of the amplitude of the current in the active cathodic phase. The voltage across R1 (100e) is used to monitor the biphasic current through the electrodes. CAC is a F low-leakage polyester capacitor, RDC is a high-precision 107 ke resistor and the voltmeter is an HP 34401A 6-digit multimeter which has 10 M input resistance. The current waveform is low-pass filtered by the combined resistance and capacitance (time constant 7.4 s) and the direct current is the measured voltage divided by 105.9 k. Each of the two U-shaped Pt electrodes in the book had an area of about 7 mm. A Pt electrode has a maximum charge density of 0.15 mC/cm. The charge density in the experiment was only about 10% of the maximum value.
Fig.21
To be consistent with the previous specification, the leading cathodic current pulse was always 1 mA and 1 ms while the inter-phase delay and the inter-cycle delay (between anodic phase and next cycle’s cathodic phase) were always kept at 1 ms. Table V shows the measured direct current for different stimulation rates and amplitudes of the initial current in the passive anodic phase. As shown, the direct current increases with increasing stimulation rate and decreasing amplitude of the initial current in the passive cathodic phase, but are never higher than 12.2 nA. To our knowledge, FES never uses frequencies higher than 50 Hz so this is a worst-case condition and corresponds to leakage of 0.024% of the charge in the stimulation pulse. This result shows that passive discharging without any large blocking-capacitors but relying only on the capacitance of the Pt electrodes can give satisfactory results. With a 30F polyester blocking-capacitor added in the test circuit, the measured direct current was reduced to about 2 nA.
Fig.22
5.5 Stimulation of Frog Nerve in Vitro
Finally, to verify the practical working of our HFCS stimulator chip, we performed an in vitro experiment on the sciatic nerve of a frog in Ringer’s solution. The stimulating electrode used was a tripolar book electrode, configured as a dipole, while the recording electrode was a dipole hook electrode (inhouse made). The recording amplifier was an ISO-DAM8A by World Precision Instruments. For these experiments the stimulator analog power supply was set to 6 V. The tank setup for this experiment is shown in Fig. 22 where we can see the frog nerve in the middle, the book electrode on the left and the recording hook electrode on the right.
Fig.23 shows an example of the action potential recorded at the output of the recording amplifier (amplifier gain of 10). For this recording, the stimulus pulse generated by our stimulator chip was a 1 ms, 1mAstimulation phase and 10 ms recuperation phase, separated by 1 ms inter-phase delay. The stimulation ran at 20 Hz. The HFCS switching signal and the ac-coupled oscillating discharging signal were 10 and 1 MHz, respectively. The measured average power consumption of the stimulator output stage was 200 W (using an external power supply), a fifth of which was due to the HFCS switching and ac-coupled oscillation. The average power at the stimulation load was measured to be 72 W. Hence, for this stimulation the power efficiency was 36%. Fig. 24 shows the strength-duration5 curve obtained using our stimulator chip. We noted no appreciable difference between the nerve stimulation thresholds obtained using our HFCS stimulator chip and using a conventional stimulator with a large off-chip blocking-capacitor
6. CONCLUSION
We have introduced two circuit techniques to miniaturize the output stage of implantable neural stimulators. The first technique is a new current generator circuit with major advantages over previous works. The circuit utilizes MOS transistors in the deep triode region as linearized voltage-controlled resistors and features high linearity, small voltage compliance, high output impedance and small implementation area. The second technique is a new stimulator output stage circuit with on-chip blocking-capacitor protection. The circuit utilizes the HFCS technique which allows the physical size of the stimulator implant to be dramatically reduced and still be fail-safe. To verify the circuit ideas we have implemented a four-channel stimulator chip in XFAB’s 1- m SOI CMOS technology and tested it in vitro. The benefits of miniaturization offered by the proposed techniques are a major step towards developing a high-density neural stimulation interface for the lumbro-sacral spinal roots. It is hoped that this will restore many more functions to people with spinal cord injury than is currently possible.
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