22-02-2009, 01:06 AM
1. INTRODUCTION
GLOBAL Positioning System (GPS) receivers for the consumer market require solutions that are compact, cheap, and low power. Manufacturers of cellular telephones, portable computers, watches, and other mobile devices are looking for ways to embed GPS into their products. Thus, there is a strong motivation to provide highly integrated solutions at the lowest possible power consumption. GPS radios consist of a front-end and a digital baseband section incorporating a digital processor. While for the baseband processor, cost-reduction reasons dictate the use of the most dense digital CMOS technology, for the front-end, the best option in terms of power consumption is a SiGe BiCMOS technology.
This explains why several commercial GPS radios consist of dual or multichip systems using the best technology option for the front-end and baseband processor. On the other hand, the implementation of a stand-alone GPS radio into a single chip in CMOS technology is appealing in terms of cost, and would speed up the integration of GPS capabilities into mobile products. This motivated the development of GPS macro blocks and radios in CMOS technology [1], [2].
However, the cost effectiveness of this solution depends on both reduction of external components and die area of the GPS radio. Since the silicon area of RF CMOS circuits, including on-chip inductors, does not shrink at the same rate as technology scaling, the reduction of the total cost poses a severe challenge.
This paper describes the design and measurement of a fully integrated CMOS GPS receiver targeting active antenna applications with an architecture geared to highest integration and minimal silicon area at the lowest possible power consumption (i.e., comparable to the best ones available [1], [2]).
The paper is organized as follows. The GPS system, architecture, and specifications are summarized in Section II, and the chip design is reported in Section III. Implementation details and experimental measurements are reported, respectively, in Sections IV and V. Finally, in Section VI, conclusions and comparison with the state of the art are given.
2. ARCHITECTURE AND SPECIFICATIONS
The GPS signal code is a direct-sequence spread spectrum, and the type of spread spectrum employed by GPS is known as binary phase-shift keying direct-sequence spread spectrum (BPSK DSSS). In a spread-spectrum system, data are modulated onto the carrier such that the transmitted signal has a larger bandwidth than the information rate of the data. The term direct sequence is used when the spreading of the spectrum is accomplished by phase modulation of the carrier.
The GPS satellites broadcast signals in a 20 MHz-wide band (L1 band) centered at 1.575 GHz. Two DSSS signals are broadcast in this band. They are known as the P code (or precision code) and the C/A code (or coarse acquisition code) (Fig.1).
For the GPS C/A code channel, most of the signal energy is located in a 2-MHz band which lies at the middle of the 20-MHz GPS-P code channel. At the antenna of a GPS receiver, the received signal power is typically 130 dBm. In the 2-MHz main lobe of the C/A code, the noise power (KTB) is 111 dBm with an associate signal-to-noise ratio (SNR) at the antenna of 19 dB.
In the past, several architectures have been used to relax the constraints of the GPS receiver using off-chip filtering and external components. For instance, a dual-conversion architecture with a first IF between 100“200 MHz and a second close to dc relaxes the constraints between selectivity and sensitivity of the receiver, i.e., allows using an external filter in front of the GPS low noise amplifier (LNA) with a lower quality factor. However, this comes with a penalty in terms of power consumption (two downconversions and IF section running at high frequency) or in terms of bill of materials, since external IF filtering would be required. Another possibility is to use a single IF at a lower frequency with high quality factor off-chip RF filtering in front of the receiver. Clearly, the use of external components allows reducing the burden of the on-chip GPS receiver, and so its power consumption. Since we target a high level of integration, low-IF or zero-IF architecture with integrated IF filters must be selected. However, the presence of most of the energy at the center of the spectrum makes the use of a zero-IF architecture for a CMOS implementation difficult, due to the presence of flicker noise. For this reason, a low-IF architecture with image rejection has been selected in order to relax constraints on the external RF filter and to reduce the noise figure (NF) of the receiver. The associate penalty is an increased complexity and power consumption. An IF below 10 MHz guarantees a low energy at the image frequency and the feasibility of an integrated IF filters at a relatively low power consumption. Choosing an IF of 9.45 MHz, the required rejection is about 30 dB.
(Download Full Report And Abstract)[/size][/color][/url]
