30-10-2012, 11:01 AM
dear sir,
i am looking for vhdl code of error tolerant adder please help.
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free vhdl code error tolerant adder
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dear sir,
i am looking for vhdl code of error tolerant adder please help.
28-02-2013, 10:26 PM
dear sir,
i am looking for vhdl code of error tolerant adder please help.
i am looking for vhdl code of error tolerant adder please help.
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23-09-2015, 02:38 PM
free vhdl code error tolerant adder
In conventional digital VLSI design, one usually assumes that a usable circuit/system should always provide definite and accurate results. But in fact,
such perfect operations are seldom needed in our nondigital worldly experiences. The world accepts “analog computation,” which generates “good
enough” results rather than totally accurate results (Breuer, 2005). The data processed by many digital systems may already contain errors.
In many applications, such as a communication system, the analog signal coming from the outside world must first be sampled before being converted to
digital data. The digital data are then processed and transmitted in a noisy channel before converting back to an analog signal. During this process, errors may occur anywhere. Furthermore, due to the advances in transistor size scaling, factors such as noise and process variations which are previously insignificant are becoming important in today’s digital IC design International Technology Roadmap for Semiconductors. Based on the characteristic of digital VLSI design, some novel concepts and design techniques have been proposed. The concept of Error Tolerance (ET) (Breuer and Zhu, 2006; Breuer et al., 2004; Breuer, 2004; Lee et al., 2005; Chong and Ortega, 2005; Chung and Ortega, 2005; Kuok, 1995; Hsieh et al., 2007) and the PCMOS technology (Palem, 2005; Cheemalavagu et al., 2004; Korkmaz et al., 2006) are two of them. According to the definition, a circuit is error tolerant if: (1) it contains defects that
cause internal and may cause external errors and (2) the system that incorporates this circuit produces acceptable results. The “imperfect” attribute seems to
be not appealing. However, the need for the errortolerant circuit (Breuer and Zhu, 2006; Breuer et al., 2004; Breuer, 2004; Lee et al., 2005; Chong and
Ortega, 2005; Chung and Ortega, 2005; Kuok, 1995; Hsieh et al., 2007) was foretold in the 2003 International Technology Roadmap for Semiconductors (ITRS) International Technology Roadmap for Semiconductors. To deal with errortolerant problems, some truncated adders/multipliers have been reported (Stine et al., 2005; Van and Yang, 2005) but are not able to perform well in its speed, power, area, or accuracy. The “flagged prefixed adder” (Stine et al., 2005) performs better than the nonflagged version with a 1.3% speed enhancement but at the expense of 2% extra silicon area. As for the “low-error area-efficient fixed-width multipliers” (Van and Yang, 2005), it may have an area improvement of 46.67% but has average error reaching 12.4%.Of course, not all digital systems can engage the error-tolerant concept. In digital systems such as control systems, the correctness of the output signal is extremely important and this denies the use of the error tolerant circuit.
In conventional digital VLSI design, one usually assumes that a usable circuit/system should always provide definite and accurate results. But in fact,
such perfect operations are seldom needed in our nondigital worldly experiences. The world accepts “analog computation,” which generates “good
enough” results rather than totally accurate results (Breuer, 2005). The data processed by many digital systems may already contain errors.
In many applications, such as a communication system, the analog signal coming from the outside world must first be sampled before being converted to
digital data. The digital data are then processed and transmitted in a noisy channel before converting back to an analog signal. During this process, errors may occur anywhere. Furthermore, due to the advances in transistor size scaling, factors such as noise and process variations which are previously insignificant are becoming important in today’s digital IC design International Technology Roadmap for Semiconductors. Based on the characteristic of digital VLSI design, some novel concepts and design techniques have been proposed. The concept of Error Tolerance (ET) (Breuer and Zhu, 2006; Breuer et al., 2004; Breuer, 2004; Lee et al., 2005; Chong and Ortega, 2005; Chung and Ortega, 2005; Kuok, 1995; Hsieh et al., 2007) and the PCMOS technology (Palem, 2005; Cheemalavagu et al., 2004; Korkmaz et al., 2006) are two of them. According to the definition, a circuit is error tolerant if: (1) it contains defects that
cause internal and may cause external errors and (2) the system that incorporates this circuit produces acceptable results. The “imperfect” attribute seems to
be not appealing. However, the need for the errortolerant circuit (Breuer and Zhu, 2006; Breuer et al., 2004; Breuer, 2004; Lee et al., 2005; Chong and
Ortega, 2005; Chung and Ortega, 2005; Kuok, 1995; Hsieh et al., 2007) was foretold in the 2003 International Technology Roadmap for Semiconductors (ITRS) International Technology Roadmap for Semiconductors. To deal with errortolerant problems, some truncated adders/multipliers have been reported (Stine et al., 2005; Van and Yang, 2005) but are not able to perform well in its speed, power, area, or accuracy. The “flagged prefixed adder” (Stine et al., 2005) performs better than the nonflagged version with a 1.3% speed enhancement but at the expense of 2% extra silicon area. As for the “low-error area-efficient fixed-width multipliers” (Van and Yang, 2005), it may have an area improvement of 46.67% but has average error reaching 12.4%.Of course, not all digital systems can engage the error-tolerant concept. In digital systems such as control systems, the correctness of the output signal is extremely important and this denies the use of the error tolerant circuit.
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