Multiplication is an important fundamental function in the operation of arithmetic logic. Since, multiplication dominates the execution time of most DSP algorithms therefore, the high-speed multiplier is much desired. Currently, multiplication time remains the dominant factor in determining the instruction cycle time of a DSP chip. With an increasing search for greater computing power in mobile-operated mobile devices, the design emphasis has shifted from optimizing the size of the conventional delay time area to minimizing power dissipation while maintaining high throughput. The low-power, high-speed VLSI can be implemented with different types of logic. The three important considerations for VLSI design are power, area and delay. There are many proposed logic (or) low power and high speed dissipation and each logic style has its own advantages in terms of speed and power. Fast multipliers are a key theme in the VLSI design of high-speed processors. Most of the multipliers were designed using primarily logic-step transistor circuits. Pass Transistor Logic is chosen to implement most of the logic function within the multiplier. In arithmetic macros design, Pass Transistor Logic requires fewer devices to implement the basic logic function in the arithmetic operation compared to the CMOS; It is one of the important advantages of Pass Transistor Logic over CMOS. This translates into lower gateway capacity and power dissipation compared to static CMOS. The multiplier simultaneously adds the partial product bit generated with the accumulator bit. The logic of the step transistor is reported as another alternative logic that can improve circuit performance. Since it can propagate signals using both the source and the gate, its high functionality can reduce the number of transistors in terms of multiplexing control input technique, which produces a high performance in the critical path. Since a PTL based circuit can consist of only one type of MOS transistor (usually an nMOS transistor), it has a low node capacitance. As a result, PTL allows high speed and low power circuits. A core operation in real circuits, especially in digital signal processing such as filtering, modulation or processing of video or neural networks or satellite communication systems or graphics or control systems, etc., is multiplication. Often, the computational performance of a DSP system is limited by its multiplication performance. Traditionally, the shift and aggregate algorithm has been implemented to design however this is not suitable for the implementation of VLSI and also from the point of view of delay. Some of the important algorithms proposed in the literature for VLSI implementable rapid multiplication are booth multiplier, array multiplier and Wallace tree multiplier.
Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors, etc. The performance of a system is usually determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. In addition, it is usually the area that consumes the most. Therefore, optimization of speed and multiplier area is an important design issue. However, area and speed are often conflicting constraints, so speed improvement results mainly in larger areas. As a result, a whole spectrum of multipliers with different area velocity constraints are designed with complete parallelism. Multipliers at one end of the spectrum and serial multipliers at the other end. In the middle there are serial multipliers of digits in which single digits that consist of several bits are activated. These multipliers perform moderately in speed and area. However, the existing multipliers of digits have been affected by complicated switching systems and / or design irregularities. Radix multipliers 2 ^ n that work in digits in parallel instead of bits, carry the pipelining to the digit level and avoid most of the above problems. They were presented by M. K. Ibrahim in 1993. These structures are iterative and modular. The pipelining done at the digit level brings the benefit of constant speed of operation regardless of the size of the multiplier.
