Design of DMA Controller (ip Core) Using Vhdl (Power Aware Soc Design)
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Submitted By
Vinit Tarey

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ABSTRACT
Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, and Many IP core design software like Xilinx, Leonardo Spectrum, and Modelsim etc which can used to design ip core like DMA ,Interrupt Controller etc .These Ip core can be Power aware an Implement on soc by choosing different design technique and various modeling techniques .These all modeling technique and tolls like Xilinx ISE also provide RTL view which will help to make ip cores to used in any Processor design .Here in these project we will see an Intel 8237 dma ip core design which is using a very different kind of design technique not used up till now. So by this project we will prove that if we are trying & use various modeling techniques for designing ip cores than it may be used in various power level requirement circuits & processors & it may also power aware. These ip cores are ASIC application specific IC so we can control its power, speed, size etc to implement before on a embedded circuit. So an ip core design is an part of a Main embedded circuit and control the working of that circuit or processor.
So it must necessary to understand the design of an ip core and also how to design an ip core or what technique or strategy is been used to design an ip core.
Introduction
1.1 ip core (intellectual property)

An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array ( FPGA ) or application-specific integrated circuit ( ASIC ) for a product. As essential elements of design reuse , IP cores are part of the growing electronic design automation ( EDA ) industry trend towards repeated use of previously designed components. Ideally, an IP core should be entirely portable - that is, able to easily be inserted into any vendor technology or design methodology. Universal Asynchronous Receiver/Transmitter ( UART s), central processing units ( CPU s), Ethernet controllers, and PCI interfaces are all examples of IP cores.
IP cores fall into one of three categories: hard cores, firm cores, or soft cores. Hard cores are physical manifestations of the IP design. These are best for plug-and-play applications, and are less portable and flexible than the other two types of cores. Like the hard cores, firm (sometimes called semi-hard) cores also carry placement data but are configurable to various applications. The most flexible of the three, soft cores exist either as a netlist (a list of the logic gate s and associated interconnections making up an integrated circuit ) or hardware description language (HDL ) code. In electronic design a semiconductor intellectual property core, IP block,
IP core or logic core is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone. The term is derived from the licensing of the patent and source code copyright intellectual property rights that subsist in the design. IP cores can be used as building blocks within ASIC chip designs or FPGA logic designs.
In digital logic applications, IP cores are typically offered as generic gate netlists. The netlist is a Boolean-algebra representation (gates, standard cells) of the IP's logical function, analogous to an assembly-code listing for a high-level program application. The netlist protects the vendor against reverse engineering, while maintaining portability to multiple foundry targets. Some vendors also offer synthesizable versions of their IP cores. Synthesizable cores are delivered in a hardware description language such as Verilog or VHDL, permitting customer modification (at the functional level). Both netlist and synthesizable cores are called "soft cores", as both follow the SPR design flow (synthesis, placement and route.)
Analog and mixed-signal logic generally require a lower-level, physical description. Hence, analog IP (SERDES, PLLs, DAC, ADC, etc.) are distributed in transistor-layout format (such as GDSII.) Digital IP cores are sometimes offered in layout format, as well. Such cores, whether analog or digital, are called "hard cores" (or hard macros), because the core's application function cannot be meaningfully modified by the customer. Transistor layouts must obey the target foundry's process design rules, and hence, hard cores delivered for one foundry's process cannot be easily ported to a different process or foundry. Merchant foundry operators (such as IBM, Fujitsu, Samsung, TI, etc.) offer a variety of hard-macro IP functions built for their own foundry process, helping to ensure customer lock-in.
For digital applications, soft cores and hard cores serve different roles. Soft cores offer greater customer flexibility, while hard cores, by the nature of their low-level representation, offer better predictability in terms of timing performance and area.
IP cores in the electronic design industry have had a profound impact on the design of systems on a chip. The IP core can be described as being for chip design what a library is for computer programming or a discrete integrated circuit component is for printed circuit board design.
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to get information about the topic " dma controller" full report ppt and related topic refer the page link bellow

http://studentbank.in/report-dma-controller

http://studentbank.in/report-design-of-d...soc-design
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