DMA Controller
#1

[attachment=12599]
Introduction
A DMA Controller is a device, which takes over the system bus to directly transfer information from one part of the system to another. This is necessary because often blocks of data have to be moved very rapidly, sometimes at speeds even faster than is practical, if each byte were to move through the CPU. For example, displaying pictures on a video screen requires a complete scan (one frame) of the screen 30 times a second or a half scan (one field) every 60 seconds. Suppose we wish to display a black and white picture that has 256 horizontal and 240 vertical dots, which are either on or off. Such a medium-resolution picture is usually scanned once every field and thus twice every frame. In this way each dot will actually appear as a double dot on the screen, and the whole picture will be scanned 60 times a second. Now 256 by 240 dots will require 61440 bits of information or 7680 bytes. Scanning through all of these 60 times a second means that there is a little over 2 microseconds to scan each byte. Each time the byte is scanned it has to be fetched from memory. This would be a complete waste of time for the processing power of the CPU.
For the computer to be efficient, it needs special circuitry to read these bytes. One solution is to store these bytes in a special display memory with built-in scanning circuitry and an arbitration scheme between the memory accesses by the scanning circuitry and memory accesses by the CPU. (This solution is mostly used today by the use of Video RAM – VRAM.) This is sometimes called a frame buffer. The memory in such a system is said to be dual ported because there are two different ways to access it.
In contrast, one of the first low-cost systems stored these bytes in regular memory (single ported) and the scanning circuitry consisted mainly of a device called a DMA controller which actually took over the bus and generated it own address and controlled information on the system’s bus. The Dazzler actually had only about a third of the resolution in this example and it was designed to work with a clock speed of about 2 megahertz, but this presents a timing problem very comparable to the one in the example.
Because of the narrow or impossible timing constrains, DMA as described above is not recommended for direct scanning of regular memory for video display, but is the preferred method for making quick transfers of information. For example, DMA is often used when a picture or part of a picture needs to be moved quickly between a frame buffer and regular memory, or when the contents of buffers for a floppy disk need to be quickly transferred to new locations.
In general a DMA controller is used as follows: The DMA controller is told to make a transfer either by the CPU or some special circumstances; then the DMA controller makes a request to gain control of the bus from the CPU, other processors, or controllers which might currently be using bus; these other devices then relinquish control of the bus by putting their lines into tri-state condition ; they then grant the bus to the DMA controller; and finally, the DMA controller takes over the bus, generating its own address and control signals for the bus and causing the transfer of information.
The Intel 82357 DMA Controller is used to perform DMA transfers. It comes with 40-pin package. The 82357 DMA Controller can provide service for a total of four different devices at once. For example, on 82357 DMA Controller might be handling transfers for two different CRT (Cathode Ray Tube) displays, a floppy-disk controller and a magnetic tape unit. Each device is assigned a channel in the 82357. By connecting several DMA chips together, any number of channels can be supported at once. The 82357 has registers to keep track of source and destination addresses, counts and masks, and commands and status. The 82357 is programmed by writing I/O bytes to special command and mode registers. Many options are available including timing, priority schemes, and location, size and type of transfer.
A special, compressed timing mode is available in which transfers are made in just two cycles.Priority schemes are important. For example, if a DMA transfer is being made for a video display, then the DMA transfer should always take precedence over the CPU. Otherwise, blank spots will frequently appear on the screen.
You can make transfers whose source or destination is either a fixed I/O port or a block of memory. If the source or destination is in memory, then the address is automatically incremented (or decremented) after each access (byte move). If the source or destination is an I/O port, then the address should remain constant during the transfer.
The 82357 has a very useful feature called auto initialization When you select this, you automatically restore parameters (such as beginning address and count) for a channel after the transfer is completed. This way you can repeat the same action without needing to update the old counter parameters in the chip
Reply
#2

to get information about the topic " dma controller" full report ppt and related topic refer the page link bellow

http://studentbank.in/report-dma-controller

http://studentbank.in/report-design-of-d...soc-design
Reply

Important Note..!

If you are not satisfied with above reply ,..Please

ASK HERE

So that we will collect data for you and will made reply to the request....OR try below "QUICK REPLY" box to add a reply to this page
Popular Searches: dma controller block body diagram ppt, dma controller implementation, dma engine, dma controller 8, dma controller 8257 pin diagram, design of dma controller ip core using vhdl power aware soc design, 8257 dma controller usings fpga,

[-]
Quick Reply
Message
Type your reply to this message here.

Image Verification
Please enter the text contained within the image into the text box below it. This process is used to prevent automated spam bots.
Image Verification
(case insensitive)

Possibly Related Threads...
Thread Author Replies Views Last Post
  Design of DMA Controller (ip Core) Using Vhdl (Power Aware Soc Design) smart paper boy 1 1,550 30-11-2012, 12:47 PM
Last Post: seminar details
  Adaptive Non-linear Congestion Controller for Differentiated-Services Framework project topics 0 868 02-05-2011, 11:54 AM
Last Post: project topics
  An Observer-Based Controller Design Method for Improving Air/Fuel Characteristics of seminar class 0 904 14-02-2011, 10:12 AM
Last Post: seminar class
  remote desktop controller full report project report tiger 2 8,015 24-11-2010, 09:46 AM
Last Post: seminar surveyer
  Design of HDLC (High Level Data Link Controller) pradeepa arumugam 1 2,300 20-10-2010, 01:06 PM
Last Post: project report helper
  DATA PACKETS ANALYZER AND CONTROLLER LAN project report tiger 0 1,193 06-02-2010, 03:08 PM
Last Post: project report tiger
Wink Development of Web Based Document Version Controller computer science crazy 0 1,459 04-09-2009, 05:01 AM
Last Post: computer science crazy

Forum Jump: