Built-In Self-Test and Calibration of Mixed-Signal Devices


Outline
Introduction
Background
BIST Architecture for Mixed-Signal Devices
Overview of Proposed Architecture
Test of DAC/ADC
Calibration of DAC
Sigma-Delta Modulation
Polynomial Fitting Algorithm
Conclusion
Motivation
Digital BIST techniques
Defect-oriented
Logic BIST, scan chain, boundary scan, JTAG, etc
Mixed-Signal BIST techniques
Specification-oriented
No universally accepted standard
Issues
Parameter deviation
Process variation

Approach
Problem
Design a post-fabrication variation-tolerant process-independent technique for mixed-signal devices
Solution
Test and characterize mixed-signal devices using digital circuitry
Use DSP as BIST controller for test pattern generation (TPG) and output data analysis (ORA)
Calibrate mixed-signal devices
Mixed-Signal Devices
Both digital and analog circuitry in single die
DSP usually embedded for data processing
Analog circuitry controllable by digital part
Converters
Analog-to-digital converter (ADC)
Flash ADC, successive-approximation ADC, Pipeline ADC, Sigma-Delta ADC
Digital-to-analog converter (DAC)
PWM/Oversampling DAC, Binary-weighted DAC
Testing of Mixed-Signal Devices
Both digital and analog circuitry need test
Defects and faults
Catastrophic faults (hard faults)
Parametric faults (soft faults)
Test approaches
Functional test (specification oriented)
Structural test (defect oriented)

Digital BIST
Conventional logic BIST technology
LFSR-based random test; Scan-based deterministic test
DSP can be TPG and ORA
Digital circuitry must be fault-free before being used for mixed-signal test
May be hardware or software based

Faulty Mixed-Signal Circuitry
Good circuitry
All parameters and characteristics are within pre-defined specified range
Fault-tolerance factor
Post-fabrication and software-controllable
Trade-off between fault-tolerance of parameter deviation and calibration resolution
Larger value for wider fixing range; smaller one for better fixing results
Fault-tolerance factor may vary for different applications

Challenges
Analog circuitry
No convincing fault model
Difficult to identify faults
Device parameters more susceptible to process variation than digital circuitry
Fault-free behavior based on a known range of acceptable values for component parameters
Large statistical process variation effects in deep sub-micron MOSFET devices

Process Variation
Parameter variation in nanoscale process
Yield, reliability and cost
Feature size scaling down and performance improvement
Effects on digital and analog circuitry
Analog circuitry more affected by process variation
Parameter deviation severed in nanoscale process
System performance degraded when parameter deviation exceeds beyond tolerant limits

Outline
Introduction
Background
BIST Architecture for Mixed-Signal Devices
Overview of Proposed Architecture
Test of DAC/ADC
Calibration of DAC
Sigma-Delta Modulation
Polynomial Fitting Algorithm
Conclusion
Resolution and Non-linearity Error
Resolution: N-bit
Least significant bit (LSB)

Non-linearity errors
Differential non-linearity (DNL)
Integral non-linearity (INL)


Outline
Introduction
Background
BIST Architecture for Mixed-Signal Devices
Overview of Proposed Architecture
Test of DAC/ADC
Calibration of DAC
Sigma-Delta Modulation
Polynomial Fitting Algorithm
Conclusion
Test Architecture
Digital system
Digital I/O, digital loopback
Digital signal processor (DSP)
TPG and ORA and test control unit
Mixed-signal system
DAC and ADC, Analog loopback
Analog system
Analog circuitry
Analog signal I/O, analog I/O loopback

Available Testing Approaches
Servo-loop Method
Oscillation BIST Method
Sigma-Delta Testing Method
FFT-based Testing Method
Histogram Testing Method
Widely used for testing of on-chip ADC/DAC
Need large amount of samples and slow-gain current source
Unsuitable for high-resolution converters

Introduction
Background
BIST Architecture for Mixed-Signal Devices
Overview of Proposed Architecture
Test of DAC/ADC
Calibration of DAC
Sigma-Delta Modulation
Polynomial Fitting Algorithm
Conclusion
Testing Components
Analog Signal Generator (ASG)
Linear ramp signals
Sinusoidal signals
Measuring ADC (m-ADC)
High-resolution and high linearity
First-order single-bit Sigma-Delta ADC
Dithering DAC (d-DAC)
Low resolution and low cost
Output voltage: specified error-tolerant range
Polynomial evaluation unit
Sinusoidal Testing Signal
More complex design
Used for dynamic testing (non-linearity (IP3), dynamic range, harmonic distortion)
Fast Fourier Transformation (FFT) by DSP required
Optional in the proposed BIST approach
Testing Components
Measuring ADC (m-ADC)
First-order single-bit Sigma-Delta ADC
ENOB determined by oversampling ratio


Dithering DAC (d-DAC)
Low resolution DAC: binary-weighted
Fault-tolerance factor