Charge Trapping Effects in High-k Transistors

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Note, this is not a real abstract but a template based from the real one. Transition metal and rare-earth oxides comprise many of the high dielectric constant (high-k) materials currently being investigated for application as gate dielectrics in highly scaled transistors. A common electronic feature of these materials is the presence of d-shell states, which leads to their structural properties being drastically different from those of the conventional SiO2 gate dielectric [1, 2]. One of the high-k dielectric properties with significant implications for their electrical characteristics is a relatively high density of as-grown defects, which may function as electron traps and fixed charges. The latter can complicate the setting of symmetrical threshold voltage (Vt) values in N and P types devices, while diffusion of these charges at elevated temperature/voltage bias, as well as electron trapping/de-trapping in structural defects may contribute to threshold voltage instability and mobility degradation in transistors with the high-k gate stack.