verilog code for 32 bit vedic multiplier is required ..

hey guys , could you please send me 32 bit Vedic multiplier vhdl code or Verilog code.
thanks in advance

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hey guys , could you please send me 32 bit Vedic multiplier vhdl code or Verilog code.
thanks in advance.

yared246[at]gmail.com

32 bit vedic multiplier verilog code

Abstract

Binary multipliers and addresses are used in the design and development of Arithmetic Logic Unit (ALU), Digital Signal Processing (DSP) Processors, Multiply and Accumulate (MAC).The objective of this paper is to implement digital multipliers based on the concept of Vedic mathematics. In order to develop a digital multiplier, Urdhva-tiryakbyham sutra of Vedic mathematics is used to implement vertical and cross wise operations. Since these are digital multipliers, they are implemented on FPGA board and are tested through the 8 LED (s) in FPGA (Nexys 3). A 32-bit Vedic multiplier has been simulated in Xilinx ISE 13.4 and has been compared with a 32-bit binary multiplier.The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area. The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 14.2 and synthesis is done in both RTL compiler using cadence as well as Xilinx. The chip design for the proposed MAC is also carried out.