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Title: An Introduction to Low Power Design in VLSI
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The paper present the RF transmitter architecture based on All Digital Phase Locked
Loop (ADPLL) which is built from the ground up using digital techniques and digital
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Presented By:
D.Sairam(05631A0433)

D.Satishvarma(05631A0437)

ISTE Membership numbers: 1782 &1786
SRI VB4KATESHWARA ENGINEERING COLLEGE
SURYAPET-508 213. NALGONDA DIST.(A.P)
Accredited by NBA


Abstract:

Since the invention of the integrated circuit in 19S8,the number of processing steps required to make one has grown from Less than 10 to several hundreds. At the same time-, the silicon wafers on which the VLSI ICs. are produced have gone from being coin sized to being dinner-plate sized. ....etc

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Title: VLSI Implementation of VisibleWatermarking for a Secure Digital Still Camera Design
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Watermarking is used to embeds data(a watermark) into a multimedia object for its copyright protection. The watermarks can be perceptible where it can be seen to the user on careful inspection.In the imperceptible case, the watermark cannot be decoded without an appropriate decoding mechanism. The process of embedding a watermark in an image is a computationally intensive task. The implementation in hardware can significantly speed up this task.A new
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Title: An Introduction to Low Power Design in VLSI
Page Link: An Introduction to Low Power Design in VLSI -
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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This seminar will cover the issues and challenges of the low power design, what are the different sources of power dissipations and the degrees of freedom with the problem associated with them ....etc

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Title: low power design in vlsi
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Title: CMOS VLSI Design
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Introduction


Plenty of Room at the bottom??

Currently at 45 nm process node and soon to be on 28 nm
Lithography was seen to be a major obstacle (dealt with using Immersion or X/EUV)
Moore’s Law still holding but for how long?
Transistors on die doubling and so is the Fab cost (Standing at close to 5bn for latest tech)

Materials Innovations

STI (Shallow Trench Isolation), CMP (Chemical Mechanical Polishing) and other process enhancements are now part of all man ....etc

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