Prepared By –
ANUPAM MURMU
ASHUTOSH GANDHEWAR
KUSHAL MURARI

WASTE MATERIAL MANAGEMENT IN CONSTRUCTION INDUSTRY TO MINIMIZE POLLUTION (FULL REPORT)
OBJECTIVE
Green building (sustainable building) refers to a structure and using process that is environmentally responsible and resource-efficient throughout a building's life-cycle: from siting to design, construction, operation, maintenance, renovation, and demolition. This practice expands and complements the cl ....etc

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DG Allocation Using an Analytical Method to Minimize Losses and to Improve Voltage Security
Abstract
This paper proposes an analytical method for
optimal allocation and sizing of Distributed Generation
(DG) units in order to minimize losses and to improve the
voltage profile in distribution systems. The evaluation of
losses and voltage profile is based on a power flow method
for radial networks. The approach, which is based on the
calculation of losses sensitivity factor, has been applied to
IEEE 13 and 37 bus distribut ....etc

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A Mini project On
COMPLETE SELFPROTECTION TECHNOLOGY TO MINIMIZE THE FAILURES OF DISTRIBUTION TRANSFORMER
Presented By :
Mr. P. Vinay kumar 06M21A0257
Mr. K. Susheel kumar 06M21A0251
Mr. G.Manikanta 06M21A0210
ELECTRICAL AND ELECTRONIC ENGINEERING

PROFILE OF VIJAI ELECTRICALS
Vijai Electricals is a 1300 Crore Company with an ISO 9001 Certification. It is the countrys largest manufacturer of Single Phase and Three Phase Oil Filled and Cast Resin Distribution Transformers (primary and secondary) upto 10 M ....etc

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documentation and absract for failure of distribution transformers and remedial solutions ....etc

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what are drawbacks in existing system
and advantages of praposed system ....etc

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I want report on shaft and axle failure and ppt for same for electric loco shed Kanpur ....etc

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PRESENTED BY
S.ELANGO
P.C. KISHORE KUMAR


A 130nm CMOS to Minimize area and quantization noise in frequency synthesizer using offset PLL
ABSTRACT
 It achieves low-noise .
 OPLL highly suppresses the quantization noise from the delta-sigma modulator.
 It consumes low power by employing charge-recycling
technique in the sub-PLL.
 Synthesizer implemented in 0.13 ȗm
 CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of po ....etc

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