Abstract
In this paper, we review the logical effort model presented in . Based on the HSPICE simulation results using 0.18/Jm, CMOS technology as applied to logic blocks used in arithmetic circuits; we analyze the efficiency of the model and also present modifications that include modeling of wire delay. We propose a new model for logical effort that will better fit the behavior of these blocks. The results are applicable for evaluation of arithmetic units as well as for development of new arithmetic algorithms. Our ultimate objective is ....etc

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import java.applet.*;
import java.awt.*;
import java.awt.event.*;
import java.awt.Choice.*;
//
public class Awte extends Applet implements TextListener,ActionListener
{
int a,b,c;
String s;
TextField f1,f2,f3;
Label l1,l2,l3;
Button Add,Sub,Mul,Div;
public void init()
{
//setBackground(Color.green);
setForeground(Color.red);
l1=new Label(First number);
l2=new Label(Second number);
l3=new Label(Result);
f1=new TextField(10);
f2=new Te ....etc

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ppt on parallel decimal multiplicatio algorithm ....etc

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To make presentation on the requested topic ....etc

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High-Speed VLSI Arithmetic Units: Adders and Multipliers


Introduction

Digital computer arithmetic is an aspect of logic design with the objective of developing
appropriate algorithms in order to achieve an efficient utilization of the available hardware .
Given that the hardware can only perform a relatively simple and primitive set of Boolean
operations, arithmetic operations are based on a hierarchy of operations that are built upon the
simple ones. Since ultimately, speed, power and chip area ar ....etc

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Improved Design of High-Performance Parallel Decimal Multipliers
The efficient implementations of parallel decimal multipliers is demanded by the new generation of high-performance decimal floating-point units (DFUs). The architectures of two parallel decimal multipliers is described in this chapter. signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples is used to perform the parallel generation of partial products. The partial products are t ....etc

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I request to provide details about 'Improved Design of High-Performance
Parallel Decimal Multipliers'.The coding of 4221&5211,vhdl code for 16:2 tree csa ans 32:2 csa and help to make seminar report and ppt ....etc

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could you please send me the lex program to specify decimal numbers ....etc

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I want VHDL cod for parallel decimal multiplier ....etc

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1. INTRODUCTION
An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic and logic operations on the operands in computer instruction words. In some processors, the ALU is divided into two units, an arithmetic unit (AU) and a logic unit (LU). Some processors contain more than one AU - for example, one for fixed-point operations and another for floating-point operations.
Generally ar ....etc

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