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Title: PERFORMANCE STUDY OF MULTILEVEL TAG-CHECK FULLY ASSOCIATIVE CACHE
Page Link: PERFORMANCE STUDY OF MULTILEVEL TAG-CHECK FULLY ASSOCIATIVE CACHE -
Posted By: nit_cal
Created at: Saturday 31st of October 2009 06:55:40 PM
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PERFORMANCE STUDY OF MULTILEVEL TAG-CHECK FULLY ASSOCIATIVE CACHE ....etc

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Title: Design and Implementation of BUILT IN SELF TEST BIST
Page Link: Design and Implementation of BUILT IN SELF TEST BIST -
Posted By: project report helper
Created at: Monday 27th of September 2010 06:15:35 PM
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Design and Implementation of BUILT IN SELF TEST (BIST)

Abstract

The increasing growth of sub-micron technology has resulted in the difficulty of testing. Design and test engineers have no choice but to accept new responsibilities that had been performed by groups of technicians in the previous years. Design engineers who do not design systems with full testability in mind open themselves to the increased possibility of product failures and missed market opportunities. BIST is a design technique that allows a circ ....etc

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Title: Built-In Self-Test and Calibration of Mixed-Signal Devices
Page Link: Built-In Self-Test and Calibration of Mixed-Signal Devices -
Posted By: project uploader
Created at: Wednesday 07th of March 2012 02:49:41 PM
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Built-In Self-Test and Calibration of Mixed-Signal Devices


Outline
Introduction
Background
BIST Architecture for Mixed-Signal Devices
Overview of Proposed Architecture
Test of DAC/ADC
Calibration of DAC
Sigma-Delta Modulation
Polynomial Fitting Algorithm
Conclusion
Motivation
Digital BIST techniques
Defect-oriented
Logic BIST, scan chain, boundary scan, JTAG, etc
Mixed-Signal BIST techniques
Specification-oriented
No universally accepted standard
Issues
Parameter deviation
Process variation

App ....etc

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Title: Built In Self Test of FPGA
Page Link: Built In Self Test of FPGA -
Posted By: renuprasad.rvpb
Created at: Tuesday 14th of June 2011 06:40:24 PM
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Hi.. I m Prasad MC, can anyone please send me the report and code for Built In Self Test of Configurable Logic Blocks of FPGA.... Thank you..... ....etc

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Title: TAG-soft shell mobile phones
Page Link: TAG-soft shell mobile phones -
Posted By: praisysarum
Created at: Sunday 19th of September 2010 06:02:40 PM
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Title: tag soft shell
Page Link: tag soft shell -
Posted By: allisha
Created at: Tuesday 05th of October 2010 09:30:33 PM
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Title: SUPER RF TAG AND LOCAL AREA WIRELESS NET WORK APPLIED IN SUPERMARKET FOR ITEM SEARCHI
Page Link: SUPER RF TAG AND LOCAL AREA WIRELESS NET WORK APPLIED IN SUPERMARKET FOR ITEM SEARCHI -
Posted By: computer science crazy
Created at: Friday 18th of September 2009 12:20:25 AM
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SUPER RF TAG AND LOCAL AREA WIRELESS NET WORK APPLIED IN SUPERMARKET FOR ITEM SEARCHING, LOCALIZATION GUIDE AND PURCHASE GOODS ACCESS AND AUTOMATIC BILL REGISTRATION IN REAL TIME.


ABSTRACT : The active RFID technology is gaining strong support from business for various applications such as supply chain management, access control, and in luggage management, etc due to the cost consideration, it is still not a replacement for the traditional item-level Bar-code. Therefore, tracking and analyzing the shopping path and purchasing behaviors of ....etc

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Title: TAG-soft shell mobile phones
Page Link: TAG-soft shell mobile phones -
Posted By: praisysarum
Created at: Sunday 19th of September 2010 06:14:54 PM
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Title: BUILT IN SELF TEST FOR A CMOS ALU
Page Link: BUILT IN SELF TEST FOR A CMOS ALU -
Posted By: computer science crazy
Created at: Friday 18th of September 2009 12:26:27 AM
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BUILT IN SELF TEST FOR A CMOS ALU

Abstract:- A technique is proposed for implementing BIST (built-in self-test) in a CMOS arithmetic and logic unit (ALU). The approach covers single stuck-open faults and all functional faults that do not induce memory effects. The specific fault set covered by the test includes: (1) all single stuck-open faults on n and p transistors anywhere in the ALU (F1 faults); and (2) all functional faults that affect any single-bit slice of the (F2 faults), a functional fault being any fault that changes one combinati ....etc

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Title: reliability bit built in test doc
Page Link: reliability bit built in test doc -
Posted By:
Created at: Wednesday 21st of November 2012 02:50:27 AM
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I want paper presentation on built in test intelligence system design or any other topic related to it... Please provide it on my gmail account [email protected]...

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