08-02-2010, 10:06 AM
LOW POWER VLSI On CMOS
Submitted by:
K.Nagendra
Why we go to Low Power..
PORTABILITY:
Enhanced run-time, Reduced weight, Reduced volume, Low cost operation
High Performance:
Low-cost cooling, Low-cost packaging, Low-cost operation
RELIABILITY:
Avoid thermal problems
Avoid scaling related problems
Where Does Power Go In CMOS
Dynamic Power Consumption : Charging and Discharging Capacitors
Short Circuit Currents : Short circuit path
between supply rails during switching
Leakage: Leakage diodes and
transistors
Ptotal = PDYN + PSC + PLeakage
=CLVDDF+VDDIPEAK{(Tr + Tf)/2}F+VDD ILEAK
Glitching¦
Glitching refers to spurious and unwanted transitions that occur before a node settle down to its final steady-state value.
Glitching often arises when paths with unbalanced propagation delay converges at the same point in the circuit.
The dissipation caused by the spurious transitions can reach up to 25% of the total dissipation for some circuits.
Short Circuit Currents
Short circuit currents are encountered only in static design.
In static CMOS circuits the flow current from VDD to GND during Switching when both NMOS and PMOS conducting Simultaneously.
Such path never exists in a dynamic circuits.
Short-Circuit energy as a function of slope ratio
Short-Circuit energy dissipation (normalized with respect to zero i/p rise time energy) for a static CMOS.
The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals.
Short-Circuit reduced by lower the Supply Voltage.
Conclusion
Thus the low power can be achieved by decreasing Vdd to certain level.
As leakage current cannot be reduced, the short circuit currents are eliminated by dynamic circuits.
The power dissipation due to short circuit currents is minimized by matching the rise/fall times of the input and output signals
Glitching makes power to dissipate so it is reduced by cope process
