28-01-2010, 06:23 PM
a) Processor and the Reconfigurable Logic on an FPGA
b) Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers
c) A Novel Multiplexer-Based Low-Power Full Adder
d) Registers for Phase Difference Based Logic
e) Logical Reversibility of Computation
f) Reconfigurable Architecture for Network Flow Analysis
g) The Reconfigurable Instruction Cell Array
h) Cost-Efficient SHA Hardware Accelerators
i) Fast Elliptic Curve Cryptography on FPGA
j) System Architecture and Implementation of MIMO Sphere Decoders on FPGA
k) Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
l) A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
m) A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System
n) Blind Separation of Superimposed Shifted Images Using Parameterized Joint Diagonalization
o) Efficient Communication Between the Embedded
p) A coding framework for low power address and data busses
q) Spread Spectrum Signaling for Speech Watermarking
r) A Lightweight Encryption Method Suitable For Copyright Protection
s) A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture
t) Concurrent Error Detection in Reed“SolomonEncoders and Decoders
u) VLSI Implementation of Multiplier-Free Low Power Baseband Filter for CDMA Systems
b) Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers
c) A Novel Multiplexer-Based Low-Power Full Adder
d) Registers for Phase Difference Based Logic
e) Logical Reversibility of Computation
f) Reconfigurable Architecture for Network Flow Analysis
g) The Reconfigurable Instruction Cell Array
h) Cost-Efficient SHA Hardware Accelerators
i) Fast Elliptic Curve Cryptography on FPGA
j) System Architecture and Implementation of MIMO Sphere Decoders on FPGA
k) Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
l) A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
m) A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System
n) Blind Separation of Superimposed Shifted Images Using Parameterized Joint Diagonalization
o) Efficient Communication Between the Embedded
p) A coding framework for low power address and data busses
q) Spread Spectrum Signaling for Speech Watermarking
r) A Lightweight Encryption Method Suitable For Copyright Protection
s) A C-based Algorithm Development Flow for a Reconfigurable Processor Architecture
t) Concurrent Error Detection in Reed“SolomonEncoders and Decoders
u) VLSI Implementation of Multiplier-Free Low Power Baseband Filter for CDMA Systems
