VLSI Design and Implementation of Low Power MAC Unit with Block Enabling Technique

[seminar class]

Abstract
In the majority of digital signal processing (DSP) applications the critical operations
are the multiplication and accumulation. Real-time signal processing requires high speed
and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which
is always a key to achieve a high performance digital signal processing system. The
purpose of this work is, design and implementation of a low power MAC unit with block
enabling technique to save power. Firstly, a 1-bit MAC unit is designed, with appropriate
geometries that gives optimized power, area and delay. The delay in the pipeline stages in
the MAC unit is estimated based on which a control unit is designed to control the data
flow between the MAC blocks for low power. Similarly, the N-bit MAC unit is designed
and controlled for low power using a control logic that enables the pipelined stages at
appropriate time. The adder cell designed has advantage of high operational speed, small
transistor count and low power. The MAC is implemented on a 0.18um CMOS technology
using CADENCE VIRTUOSO tool. This paper also investigates on various architectures of
multipliers and adders which are suitable for implementation of high throughput signal
processing and at the same time to achieve low power consumption. The whole MAC chip
is operated at 125 MHz using 1.8 V power supply. The power is reduced by 27% using the
block enabling technique compared to the normal design.
Keywords: Low Power, MAC, clock gating, block enable, multiplier.
1. Introduction
In the majority of digital signal processing (DSP) applications the critical operations usually involve
many multiplications and/or accumulations. For real-time signal processing, a high speed and high
throughput Multiplier-Accumulator (MAC) is always a key to achieve a high performance digital
signal processing system. In the last few years, the main consideration of MAC design is to enhance its
speed. This is because, speed and throughput rate is always the concern of digital signal processing
system. But for the epoch of personal communication, low power design also becomes another main
design consideration. This is because, battery energy available for these portable products limits the
power consumption of the system. Therefore, the main motivation of this work is to investigate various
VLSI Design and Implementation of Low Power MAC Unit with Block Enabling Technique 621
pipelined multiplier/accumulator architectures and circuit design techniques which are suitable for
implementing high throughput signal processing algorithms and at the same time achieve low power
consumption. A conventional MAC unit consists of (fast multiplier) multiplier and an accumulator that
contains the sum of the previous consecutive products. The function of the MAC unit is given by the
following equation:

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